The Community for Technology Leaders
Asia and South Pacific Design Automation Conference (2000)
Yokohama, Japan
Jan. 25, 2000 to Jan. 28, 2000
ISBN: 0-7803-5973-9
TABLE OF CONTENTS
Session A1 (Special Session): University LSI Design Contest

A VLSI Implementation of the Blowfish Encryption/Decryption Algorithm (PDF)

Michael C.-J. Lin , National Tsing Hua University, Taiwan
Youn-Long Lin , National Tsing Hua University, Taiwan
pp. 1

VLSI Implementation of Rake Receiver for IS-95 CDMA Testbed using FPGA (PDF)

Oliver Leung , Hong Kong University of Science and Technology
Roger S. Cheng , Hong Kong University of Science and Technology
Chi-ying Tsui , Hong Kong University of Science and Technology
pp. 3

VLSI Implementation of a Switch Fabric for Mixed ATM and IP Traffic (PDF)

Chi-Ying Tsui , Hong Kong University of Science and Technology, Clear Water Bay
Louis Chung-Yin Kwan , Hong Kong University of Science and Technology, Clear Water Bay
Chin-Tau Lea , Hong Kong University of Science and Technology, Clear Water Bay
pp. 5

Design of Digital Neural Cell Scheduler for Intelligent IB-ATM Switch (PDF)

M. M.-O. Lee , Dongshin University, Korea
S.-J. Jeong , Chonnam National University, Korea
D.-W. Lee , Chonnam National University, Korea
J.-K. Lee , Dongshin University, Korea
Y.-C. Kim , Chonnam National University, Korea
S.-M. Lee , Dongshin University, Korea
pp. 7

Genetic Algorithm Accelerator GAA-II (PDF)

Masataka Yamane , Hiroshima University, Japan
Tetsushi Koide , The University of Tokyo, Japan
Hajime Ueno , Hiroshima University, Japan
Naoyoshi Toshine , Hiroshima University, Japan
Shin'ichi Wakabayashi , Hiroshima University, Japan
pp. 9

A Programmable Built-In Self-Test Core for Embedded Memories (PDF)

Cheng-Wen Wu , National Tsing Hua University, Taiwan
Chih-Tsun Huang , National Tsing Hua University, Taiwan
Jing-Reng Huang , National Tsing Hua University, Taiwan
pp. 11

An Algorithm for VLSI Implementation of Highly Efficient Cubic-Polynomial Evaluation (PDF)

Yihua Zhang , Fudan University, Shanghai, China
Qianling Zhang , Fudan University, Shanghai, China
Jun Yu , Fudan University, Shanghai, China
Fan Mo , Fudan University, Shanghai, China
pp. 13

Design of Self-timed Asynchronous Booth's Multiplier (PDF)

Cheong-Fat Chan , The Chinese University of Hong Kong
Pui-Lam Siu , The Chinese University of Hong Kong
Tin-Yau Tang , The Chinese University of Hong Kong
Chiu-Sing Choy , The Chinese University of Hong Kong
pp. 15

High Speed and Ultra-Low Power 16X16 MAC Design using TG techniques for Web-based Multimedia System (PDF)

Hyung-Seok Yoon , Dongshin University, Korea
Mike Myung-Ok Lee , Dongshin University, Korea
Jin -Hong Chung , Dongshin University, Korea
Seung-Min Lee , Dongshin University, Korea
pp. 17

A Smart Imager for the Vision Processing Front-End (PDF)

Mituru Homma , Hiroshima University, Japan
Takashi Morie , Hiroshima University, Japan
Makoto Nagata , Hiroshima University, Japan
Atsushi Iwata , Hiroshima University, Japan
Noriaki Takeda , Hiroshima University, Japan
pp. 19

A Binary Image Sensor with Flexible Motion Vector Detection using Block Matching Method (PDF)

Tomohiro Nezuka , University of Tokyo, Japan
Kunihiro Asada , University of Tokyo, Japan
Makoto Ikeda , University of Tokyo, Japan
Takafumi Fujita , University of Tokyo, Japan
pp. 21

An Arbitrary Chaos Generator Core Circuit Using PWM/PPM Signals (PDF)

Takashi Morie , Hiroshima University, Japan
Atsushi Iwata , Hiroshima University, Japan
Kenichi Murakoshi , Hiroshima University, Japan
Makoto Nagata , Hiroshima University, Japan
pp. 23

An Application Specific Java Processor with Reconfigurabilities (PDF)

Katsumasa Watanabe , Nara Institute of Science and Technology, Japan
Shinji Kimura , Nara Institute of Science and Technology, Japan
Kazuyoshi Takagi , Nagoya University
Tatsumori Abematsu , SHARP Corporation
Hiroyuki Kida , NIIT at Nara, Japan
pp. 25

Reconfigurable Synchronized Dataflow Processor (PDF)

Hiroaki Kobayashi , Tohoku University, Japan
Hiroshi Sasaki , Tohoku University, Japan
Nobuyoshi Shoji , Friendly Systems Co., Ltd., Japan
Tadao Nakamura , Tohoku University, Japan
Hideaki Tsukioka , Friendly Systems Co., Ltd., Japan
Hitoshi Maruyama , Tohoku University, Japan
pp. 27

Prototype Microprocessor LSI with Scheduling Support Hardware for Operating System on Multiprocessor System (PDF)

Naoki Nishimura , Hiroshima City University, Japan
Takahiro Sasaki , Hiroshima City University, Japan
Tetsuo Hironaka , Hiroshima City University, Japan
pp. 29

A 16-bit Redundant Binary Multiplier Using Low-Power Pass-Transistor Logic SPL (PDF)

Hirofumi Sakamoto , Hiroshima City University, Japan
Ken'ichiro Uda , Kobe University, Japan
Takao Tsuda , Kobe University, Japan
Hiroyuki Ochi , Hiroshima City University, Japan
Kazuo Taki , Kobe University, Japan
Bu-Yeol Lee , Kobe University, Japan
pp. 33

An 8 x 8-b nRERL Serial Multiplier for Ultra-Low-Power Applications (PDF)

Soo-Ik Chae , Seoul National University, Seoul, Korea
Joonho Lim , Global Communication Technology, Inc., CA
Sang-Chul Kang , Seoul National University, Seoul, Korea
Dong-Gyu Kim , Daewoo Electronics Ltd., Seoul, Korea
pp. 35
Session B1: IP Reuse and Protection Methods

Essential Issues for IP Reuse (Abstract)

Tom Nukiyama , NEC Corp., Japan
Allen C.-H. Wu , Tsing Hua University, Taiwan, ROC
Viraphol Chaiyakul , Y Explorations Inc., USA
Daniel D. Gajski , University of California, Irvine, USA
Shojiro Mori , Toshiba Corp., Japan
Pierre Bricaud , Mentor Graphics Corp., USA
pp. 37

Usage-Based Characterization of Complex Functional Blocks for Reuse in Behavioral Synthesis (Abstract)

Daniel D. Gajski , University of California, Irvine
Nong Fan , Y Explorations, Inc., Lake Forest, CA
Viraphol Chaiyakul , Y Explorations, Inc., Lake Forest, CA
pp. 43

Reuse and Protection of Intellectual Property in the SpecC System (Abstract)

Rainer D?mer , University of California, Irvine
Daniel D. Gajski , University of California, Irvine
pp. 49

Fair Watermarking Techniques (Abstract)

Miodrag Potkonjak , University of California, Los Angeles
Gang Qu , University of California, Los Angeles
Jennifer L. Wong , University of California, Los Angeles
pp. 55
Session C1: Decision Diagrams and Verification Methods

Automatic Partitioning for Efficient Combinational Verification (Abstract)

Rajarshi Mukherjee , Fujitsu Laboratories of America, Sunnyvale, CA
Masahiro Fujita , Fujitsu Laboratories of America, Sunnyvale, CA
Jawahar Jain , Fujitsu Laboratories of America, Sunnyvale, CA
Koichiro Takayama , Fujitsu Laboratories of America, Sunnyvale, CA
pp. 67

A Hardware Simulation Engine Based on Decision Diagrams (Abstract)

Tsutomu Sasao , Kyushu Institute of Technology, Japan
Yukihiro Iguchi , Meiji University, Japan
Munehiro Matsuura , Kyushu Institute of Technology, Japan
Atsumu Iseno , Meiji University, Japan
pp. 73

Formal Verification based on Assume and Guarantee Approach - A Case Study (Abstract)

Tsuneo Nakata , Fujitsu Laboratories Ltd., Japan
Subir K. Roy , Fujitsu Laboratories Ltd., Japan
Hiroaki Iwashita , Fujitsu Laboratories Ltd., Japan
pp. 77

Multi-Clock Path Analysis Using Propositional Satisfiability (Abstract)

Kazuhiro Nakamura , Nara Institute of Science and Technology, Japan
Shinji Maruoka , Nara Institute of Science and Technology, Japan
Shinji Kimura , Nara Institute of Science and Technology, Japan
Katsumasa Watanabe , Nara Institute of Science and Technology, Japan
pp. 81
Session D1: Routing in Deep-Submicron

Self-Reforming Routing for Stochastic Search in VLSI Interconnection Layout (Abstract)

Shigetoshi Nakatake , Kitakyushu University, Japan
Yasuhiro Takashima , Japan Advanced Inst. of Science and Technology, Japan
Yoji Kajitani , Tokyo Inst. of Technology, Japan
Yukiko Kubo , Tokyo Inst. of Technology, Japan
pp. 87

An Interconnect Topology Optimization by a Tree Transformation (Abstract)

Naofumi Tsujii , Chuo University, Japan
Katsutoshi Baba , Fujitsu Corp., Japan
Shuji Tsukiyama , Chuo University, Japan
pp. 93

Area Routing Oriented Hierarchical Corner Stitching with Partial Bin (Abstract)

Zhang Yan , Tsinghua University, P.R. China
Hong Xianlong , Tsinghua University, P.R. China
Cai Yici , Tsinghua University, P.R. China
Wang Baohua , Tsinghua University, P.R. China
pp. 105
Session A2 (Special Session): CAD for Embedded Systems

Offline Program Re-mapping to Improve Branch Prediction Efficiency in Embedded Systems (Abstract)

William H. Mangione-Smith , The University of California at Los Angeles
Stephen S. Brown , The University of California at Los Angeles
Jeet Asher , The University of California at Los Angeles
pp. 111

Timing Driven Co-design of Networked Embedded Systems (Abstract)

Ravindra Jejurikar , University of California, Irvine
Rajesh K. Gupta , University of California, Irvine
Dinesh Ramanathan , University of California, Irvine
pp. 117

Low-power Design Methodology and Applications utilizing Dual Supply Voltages (Abstract)

Kimiyoshi Usami , Toshiba Corporation, Japan
Mutsunori Igarashi , Toshiba Corporation, Japan
pp. 123

Co-synthesis with custom ASICs (Abstract)

Yuan Xie , Princeton University, NJ
Wayne Wolf , Princeton University, NJ
pp. 129
Session B2: System-Level Power Optimization & Estimation

A New Method for Constructing IP Level Power Model Based on Power Sensitivity (Abstract)

Heng-Liang Huang , National Chiao-Tung University, Taiwan
Jiing-Yuan Lin , Global UniChip Corporation, Taiwan
Jing-Yang Jou , National Chiao-Tung University, Taiwan
Wen-Zen Shen , National Chiao-Tung University, Taiwan
pp. 135

A Hybrid Approach for Core-Based System-Level Power Modeling (Abstract)

Tony D. Givargis , University of California, Riverside
Frank Vahid , University of California, Riverside
J? Henkel , NEC USA, NJ
pp. 141

Voltage Reduction of Application-Specific Heterogeneous Multiprocessor Systems for Power Minimisation (Abstract)

Sri Parameswaran , University of Queensland, Australia
Allan Rae , University of Queensland, Australia
pp. 147

Synthesis of Low Power Folded Programmable Coefficient FIR Digital Filters (Abstract)

Keshab K. Parhi , University of Minnesota, Minneapolis
Vijay Sundararajan , University of Minnesota, Minneapolis
pp. 153
Session C2: Design Environment for FPGA

Synthesis Challenges for Next-Generation High-Performance and High-Density PLDs (Abstract)

Jason Cong , University of California, Los Angeles
Songjie Xu , Aplus Design Technologies, Inc., Los Angeles
pp. 157

KressArray Xplorer: A New CAD Environment to Optimize Reconfigurable Datapath Array Architectures (Abstract)

R. Hartenstein , University of Kaiserslautern, Germany
M. Herz , University of Kaiserslautern, Germany
U. Nageldinger , University of Kaiserslautern, Germany
Th. Hoffmann , University of Kaiserslautern, Germany
pp. 163

Hardware-Software Cosynthesis for Run-time Incrementally Reconfigurable FPGAs (Abstract)

Sunghyun Lee , Seoul National University, Korea
Sungjoo Yoo , Seoul National University, Korea
Kiyoung Choi , Seoul National University, Korea
Byungil Jeong , Seoul National University, Korea
pp. 169
Session D2: Placement Consistent with Routing

Analytical Minimization of Half-Perimeter Wirelength (Abstract)

Andrew Kennings , University of Waterloo, Canada
Igor Markov , UCLA Computer Science, Los Angeles, CA
pp. 179

Modeling and Minimization of Routing Congestion (Abstract)

Majid Sarrafzadeh , Northwestern University
Maogang Wang , ECE Department, Evanston, IL
pp. 185
Session E2 (Special Session): System-In-Package (SIP)

System-In-Package (SIP): Challenges and Opportunities (Abstract)

King L. Tai , Lucent Technologies, Murray Hill, NJ
pp. 191

Taiwan Foundry for System-In-Package (SIP) (Abstract)

Albert W. Lin , APack Technologies Inc., Taiwan
pp. 197

Integration of Large-Scale FPGA and DRAM in a Package Using Chip-on-Chip Technology (Abstract)

Katsuharu Suzuki , University of California, Santa Cruz
Wayne W.-M. Dai , University of California, Santa Cruz
Michael X. Wang , University of California, Santa Cruz
Kevin J. O'conner , Lucent Technologies, Murray Hill, NJ
King L. Tai , Lucent Technologies, Murray Hill, NJ
Yee L. Low , Lucent Technologies, Murray Hill, NJ
pp. 205

Modeling and Analysis of Integrated Spiral Inductors for RF System-in-Package (Abstract)

Wayne W.-M. Dai , University of California, Santa Cruz
Minqing Liu , University of California, Santa Cruz
pp. 211
Session A3: Low Power Design : Implementation

Narrow Bus Encoding for Low Power Systems (Abstract)

Kiyoung Choi , Seoul National University, Korea
Youngsoo Shin , Seoul National University, Korea
pp. 217

Data Transmission Over a Bus with Peak-Limited Transition Activity (Abstract)

Keshab K. Parhi , University of Minnesota, Minneapolis
Vijay Sundararajan , University of Minnesota, Minneapolis
pp. 221

Power Analysis and Implementation of a Low-Power 300-MHz 8-b x 8-b Pipelined Multiplier (Abstract)

Jinn-Shyan Wang , National Chung Cheng University, Taiwan
Po-Hui Yang , National Chung Cheng University, Taiwan
pp. 225
Session B3: Embedded Software

A New Approach to Assembly Software Retargeting for Microcontrollers (Abstract)

Ing-Jer Huang , National Sun Yat-sen University, Kaohsiung, Taiwan
Dao-Zhen Chen , National Sun Yat-sen University, Kaohsiung, Taiwan
pp. 229

A Technique for QoS-based System Partitioning (Abstract)

Johnson Kin , University of California at Los Angeles
Chunho Lee , University of California at Los Angeles
William H. Mangione-Smith , University of California at Los Angeles
Miodrag Potkonjak , University of California at Los Angeles
pp. 241
Session C3: Implementation of Boolean Functions

Exact Minimization of Fixed Polarity Reed-Muller Expressions for Incompletely Specified Functions (Abstract)

Tsutomu Sasao , Kyushu Institute of Technology, Japan
Debatosh Debnath , Kyushu Institute of Technology, Japan
pp. 247

An Efficient Framework of Using Various Decomposition Methods to Synthesize LUT Networks and Its Evaluation (Abstract)

Hiroshi Sawada , NTT Communication Science Laboratories, Japan
Shigeru Yamashita , NTT Communication Science Laboratories, Japan
Akira Nagoya , NTT Communication Science Laboratories, Japan
pp. 253

Three Parameters to Find Functional Decompositions (Abstract)

Ken-ichi Kurimoto , Kyushu Institute of Technology, Japan
Tsutomu Sasao , Kyushu Institute of Technology, Japan
pp. 259
Session D3: Physical Design Planning

Delay-Optimal Wiring Plan for the Microprocessor of High Performance Computing Machines (Abstract)

Kazuhisa Miyamoto , Enterprise Server Division, HITACHI, Ltd.
Jun Kikuchi , Enterprise Server Division, HITACHI, Ltd.
Tohru Hashimoto , HITACHI Information Technology Co., Ltd.
Tetsuo Sasaki , Enterprise Server Division, HITACHI, Ltd.
pp. 265

MMP: A Novel Placement Algorithm for Combined Macro Block and Standard Cell Layout Design (Abstract)

Hong Yu , Tsinghua University, Beijing, P. R. China
Yici Cai , Tsinghua University, Beijing, P. R. China
Xianlong Hong , Tsinghua University, Beijing, P. R. China
pp. 271

Dynamic Weighting Monte Carlo for Constrained Floorplan Designs in Mixed Signal Application (Abstract)

Tianming Kong , University of California, Los Angeles
Dongmin Xu , University of California, Los Angeles
Wing Hung Wong , University of California, Los Angeles
Jun S. Liu , Stanford University, CA
Jason Cong , University of California, Los Angeles
Faming Liang , University of California, Los Angeles
pp. 277
Session E3: Methodologies for Reliable Design

Symbolic Circuit-Noise Analysis and Modeling with Determinant Decision Diagrams (Abstract)

Xiang-Dong Tan , Monterey Design Systems, Sunnyvale, CA
C.-J. Richard Shi , University of Washington, Seattle, WA
pp. 283

Gate-Level Aged Timing Simulation Methodology for Hot-Carrier Reliability Assurance (Abstract)

Lifeng Wu , BTA Technology, Inc., San Jose, CA
Nobufusa Iwanishi , Matsushita Electric Industrial Co., Ltd., Osaka, Japan
Yoshiyuki Kawakami , Matsushita Electric Industrial Co., Ltd., Osaka, Japan
Chune-Sin Yeh , BTA Technology, Inc., San Jose, CA
Alvin I-Hsien Chen , BTA Technology, Inc., San Jose, CA
Norio Koike , Matsushita Electronics Corporation, Kyoto, Japan
Ping Chen , BTA Technology, Inc., San Jose, CA
Zhihong Liu , BTA Technology, Inc., San Jose, CA
Jingkun Fang , BTA Technology, Inc., San Jose, CA
Hirokazu Yonezawa , Matsushita Electric Industrial Co., Ltd., Osaka, Japan
pp. 289

Subwavelength Lithography (PSM,OPC) (Abstract)

Tsuneo Terasawa , Hitachi Ltd., Japan
pp. 295
Session A4: Synthesis for System-On-A-Chip

Thread Partitioning Method for Hardware Compiler Bach (Abstract)

Mizuki Takahashi , Osaka University, Japan; Sharp Corporation, Japan
Nagisa Ishiura , Osaka University, Japan
Takashi Kambe , Sharp Corporation, Japan
Akihisa Yamada , Sharp Corporation, Japan
pp. 303

An Area/Time Optimizing Algorithm in High-Level Synthesis for Control-Based Hardwares (Abstract)

Tatsuo Ohtsuki , Waseda University, Japan
Nozomu Togawa , Waseda University, Japan
Masao Yanagisawa , Waseda University, Japan
Masayuki Ienaga , Waseda University, Japan
pp. 309

A Timing-Driven Synthesis of Arithmetic Circuits using Carry-Save-Adders (Abstract)

Taewhan Kim , Korea Advanced Institute of Science & Technology
Junhyung Um , Korea Advanced Institute of Science & Technology
pp. 313
Session B4: Reconfiguration Computation

Communicating Logic: An Alternative Embedded Stream Processing Paradigm (Abstract)

Kouichi Nagami , NTT Network Innovation Laboratories, Japan
Hiroshi Nakada , NTT Network Innovation Laboratories, Japan
Minoru Inamori , NTT Network Innovation Laboratories, Japan
Tsunemichi Shiozawa , NTT Network Innovation Laboratories, Japan
Hideyuki Ito , NTT Network Innovation Laboratories, Japan
Ryusuke Konishi , NTT Network Innovation Laboratories, Japan
Norbert Imlig , NTT Network Innovation Laboratories, Japan
Kiyoshi Oguri , NTT Network Innovation Laboratories, Japan
pp. 317
Session C4: Synthesis for Low Power

Power Reduction by Simultaneous Voltage Scaling and Gate Sizing (Abstract)

Chunhong Chen , Northwestern University, Evanston, IL
Majid Sarrafzadeh , Northwestern University, Evanston, IL
pp. 333

Analysis of Power-Clocked CMOS with Application to the Design of Energy-Recovery Circuits (Abstract)

Xunwei Wu , Ningbo University, China
Massoud Pedram , University of Southern California, Los Angeles
pp. 339

Low-Power Design of Sequential Circuits Using a Quasi-Synchronous Derived Clock (Abstract)

Qing Wu , University of Southern California, Los Angeles
Jian Wei , Ningbo University, China
Xunwei Wu , Ningbo University, China
Massoud Pedram , University of Southern California, Los Angeles
pp. 345

FSM Decomposition by Direct Circuit Manipulation Applied to Low Power Design (Abstract)

Jos? C. Monteiro , IST-INESC, Lisbon, Portugal
Arlindo L. Oliveira , Cadence European Labs / IST-INESC, Lisbon, Portugal
pp. 351
Session D4 (Panel Discussion): Timing Closure : The Solution and Its Problems

Timing Closure: The Solution and Its Problems (Abstract)

Ralph H. J. M. Otten , Eindhoven University of Technology, The Netherlands
pp. 359
Session E4: MOSFET Device Optimization

High Performance of Short-Channel MOSFETs due to an Elevated Central-Channel Doping (Abstract)

W. Hansch , Universit?t der Bundesweher, Germany
N. Tokida , Hiroshima University, Japan
M. Tanaka , Hiroshima University, Japan
M. Miura-Mattausch , Hiroshima University, Japan
H. J. Mattausch , Hiroshima University, Japan
T. Okagaki , Hiroshima University, Japan
pp. 365

Circuit Performance Oriented Device Optimization using BSIM3 Pre-Silicon Model Parameters (Abstract)

Shiro Kamohara , Semiconductor & Integrated Circuits, Hitachi, Ltd.
Mikako Miyama , Semiconductor & Integrated Circuits, Hitachi, Ltd.
pp. 371

Design For Manufacturability: A Path From System Level To High Yielding Chips (PDF)

Andrzej J. Strojwas , Carnegie Mellon University, Pittsburgh, PA; PDF Solutions, Inc., San Jose, CA
pp. 375
Session A5: Low Power Design : System Approach

Low-Power Silicon Architecture for Wireless Communications (Abstract)

Jan M. Rabaey , University of California at Berkeley
pp. 377

An Interleaved Dual-Battery Power Supply for Battery-Operated Electronics (Abstract)

Qing Wu , University of Southern California, Los Angeles
Massoud Pedram , University of Southern California, Los Angeles
Qinru Qiu , University of Southern California, Los Angeles
pp. 387
Session B5: System Design and Debugging

Embedded System Design with Multiple Languages (Abstract)

Ahmed Amine Jerraya , TIMA, France
Rolf Ernst , Technical University of Braunschweig, Germany
pp. 391

Symbolic Debugging of Globally Optimized Behavioral Specification (Abstract)

Miodrag Potkonjak , University of California, Los Angeles
Darko Kirovski , University of California, Los Angeles
Marios C. Papefthymiou , University of Michigan, Ann Arbor
Inki Hong , University of California, Los Angeles
pp. 397

Fast Development of Source-level Debugging System Using Hardware Emulation (Abstract)

Jun-Hee Lee , Korea Advanced Institute of Science and Technology, Korea
Chong-Min Kyung , Korea Advanced Institute of Science and Technology, Korea
Young-Su Kwon , Korea Advanced Institute of Science and Technology, Korea
Byoung-Woon Kim , Korea Advanced Institute of Science and Technology, Korea
Sang-Joon Nam , Korea Advanced Institute of Science and Technology, Korea
Kyong-Gu Kang , Medison Corporation, Korea
Yeon-Ho Im , Korea Advanced Institute of Science and Technology, Korea
pp. 401

Methodology for Hardware/Software Co-verification in C/C++ (Abstract)

Luc S?m?ria , Stanford University
Abhijit Ghosh , Synopsys Inc., Mountain View, CA
pp. 405
Session C5: Optimization Issues in Logic Synthesis

Performance-Optimal Clustering with Retiming for Sequential Circuits (Abstract)

Tzu-Chieh Tien , Tsing hua University, Taiwan
Youn-Long Lin , Tsing hua University, Taiwan
pp. 409

IBAW: An Implication-Tree Based Alternative-Wiring Logic Transformation Algorithm (Abstract)

Wangning Long , Tsinghua University, Beijing, China
Yu-Liang Wu , The Chinese University of HK, Shatin, Hong Kong
Jinian Bian , Tsinghua University, Beijing, China
pp. 415

On Mixture Density and Maximum Likelihood Power Estimation via Expectation-Maximization (Abstract)

R. Chandramouli , Iowa State University, Ames
Vamsi K. Srikantam , Hewlett Packard Labs, Palo Alto, CA
pp. 423
Session D5: Novel Techniques in Advanced Partitioning

Edge Separability Based Circuit Clustering with Application to Circuit Partitioning (Abstract)

Sung Kyu Lim , UCLA Department of Computer Science, Los Angeles, CA
Jason Cong , UCLA Department of Computer Science, Los Angeles, CA
pp. 429

Feasible Two-Way Circuit Partitioning with Complex Resource Constraints (Abstract)

Ting-Chi Wang , Chung Yuan Christian University, Chungli, Taiwan
Hsun-Cheng Lee , Chung Yuan Christian University, Chungli, Taiwan
pp. 435

Performance Driven Multiway Partitioning (Abstract)

Sung Kyu Lim , UCLA Department of Computer Science, Los Angeles, CA
Jason Cong , UCLA Department of Computer Science, Los Angeles, CA
pp. 441
Session E5: Efficient Estimation for Interconnection

Hierarchical Computation of 3-D Interconnect Capacitance using Direct Boundary Element Method (Abstract)

Jiangchun Gu , Tsinghua University, Beijing, P. R. China
Xianlong Hong , Tsinghua University, Beijing, P. R. China
Zeyi Wang , Tsinghua University, Beijing, P. R. China
pp. 447

A Simplified Hybrid Method for Calculating the Frequency-dependent Inductances of Transmission Lines with Rectangular Cross Section (Abstract)

Xiaobo Tang , Tsinghua University, Beijing
Shuzhou Fang , Tsinghua University, Beijing
Zeyi Wang , Tsinghua University, Beijing
Xianlong Hong , Tsinghua University, Beijing
pp. 453

An Analytic Calculation Method for Delay Time of RC-class Interconnects (Abstract)

Seok-Yoon Kim , Soongsil Univ., Seoul, Korea
Won-Kwang Kal , Soongsil Univ., Seoul, Korea
pp. 457

A New Efficient Waveform Simulation Method for RLC Interconnect via Amplitude and Phase Approximation (Abstract)

Xiaodong Yang , University of California, San Diego
Chung-Kuan Cheng , University of California, San Diego
Walter H. Ku , University of California, San Diego
pp. 463
Session A6: Optimized LSI Design

Optimization of VDD and VTH for Low-Power and High-Speed Applications (Abstract)

Koichi Nose , University of Tokyo, Japan
Takayasu Sakurai , University of Tokyo, Japan
pp. 469

A New CMAC Neural Network Architecture and Its ASIC Realization (Abstract)

Chien-Yuan Pao , National Chung Cheng University, Taiwan
Jinn-Shyan Wang , National Chung Cheng University, Taiwan
Kao-Shing Hwang , National Chung Cheng University, Taiwan
Yuan-Pao Hsu , National Chung Cheng University, Taiwan
pp. 481
Session B6: DSP and Memory Architecture

Retargetable Estimation Scheme for DSP Architecture Selection (Abstract)

Jan Rabaey , University of California, Berkeley
Naji Ghazal , University of California, Berkeley
Richard Newton , University of California, Berkeley
pp. 485

Data Memory Minimization by Sharing Large Size Buffers (Abstract)

Hyunok Oh , Seoul National University, Korea
Soonhoi Ha , Seoul National University, Korea
pp. 491

Array Allocation Taking into Account SDRAM Characteristics (Abstract)

Hong-Kai Chang , National Tsing Hua University, Taiwan
Youn-Long Lin , National Tsing Hua University, Taiwan
pp. 497
Session C6: Validation and Test

Causality Based Generation Of Directed Test Cases (Abstract)

Jacob A. Abraham , University of Texas at Austin
Nina Saxena , University of Texas at Austin
Avijit Saha , IBM, Austin TX
pp. 503

Fault Models and Test Generation for IDDQ Testing (Abstract)

Kozo Kinoshita , Osaka University, Japan
Yoshinobu Higami , Ehime University, Matsuyama, Japan
Kewal K. Saluja , University of Wisconsin, Madison
Yuzo Takamatsu , Ehime University, Matsuyama, Japan
pp. 509

Embedded Tutorial: Issues on SOC Testing in DSM Era (PDF)

Takashi Aikyo , Fujitsu Limited, Kawasaki, Japan
pp. 515
Session D6: Cell Generation & Process Dependent Issues

A Cell Synthesis Method for Salicide Process (Abstract)

Takashi Kambe , Sharp corporation, Japan
Takayuki Yamanouchi , Sharp corporation, Japan
Kazuhisa Okada , Sharp corporation, Japan
pp. 517

Monte-Carlo Algorithms for Layout Density Control (Abstract)

Gabriel Robins , University of Virginia, Charlottesville
Alexander Zelikovsky , Georgia State University, Atlanta
Yu Chen , UCLA Department of Computer Science, Los Angeles, CA
Andrew B. Kahng , UCLA Department of Computer Science, Los Angeles, CA
pp. 523

Layout Generation of Array Cell for NMOS 4-phase Dynamic Logic (Abstract)

Isao Shirakawa , Osaka University, Japan
Makoto Furuie , Osaka University, Japan
Yukihiro Yoshida , Osaka University, Japan
Takao Onoye , Kyoto University, Japan
Bao-Yu Song , Osaka University, Japan
pp. 529

A New Efficient Method for Substrate-Aware Device-Level Placement (Abstract)

C. Lin , Eindhoven University of Technology
D. M. W. Leenaerts , Philips Research Labs
pp. 533
Session E6: Analysis Techniques for Analog Circuits

The Enhancing of Efficiency of the Harmonic Balance Analysis by Adaptation of Preconditioner to Circuit Nonlinearity (Abstract)

M. M. Gourary , IPPM, Russian Academy of Sciences, Moscow
S. L. Ulyanov , IPPM, Russian Academy of Sciences, Moscow
S. G. Rusakov , IPPM, Russian Academy of Sciences, Moscow
K. K. Gullapalli , Motorola, Austin, TX
M. M. Zharov , IPPM, Russian Academy of Sciences, Moscow
B. J. Mulvaney , Motorola, Austin, TX
pp. 537

Analog Testability Analysis by Determinant-Decision-Diagrams based Symbolic Analysis (Abstract)

Tao Pi , University of Washington, Seattle
C.-J. Richard Shi , University of Washington, Seattle
pp. 541

A Method for Linking Process-level Varaiability to System Performances (Abstract)

Hiroaki Fujita , Kyoto University, Japan
Tomohiro Fujita , Kyoto University, Japan
Ken-ichi Okada , Kyoto University, Japan
Hidetoshi Onodera , Kyoto University, Japan
Keikichi Tamaru , Kyoto University, Japan
pp. 547
Session A7: Advanced Design Techniques for Deep-Submicron System-On-A-Chip

Design Challenges for 0.1um and Beyond (Abstract)

Takayasu Sakurai , University of Tokyo, Japan
pp. 553

Radix-4 Modular Multiplication and Exponentiation Algorithms for the RSA Public-Key Cryptosystem (Abstract)

Jin-Hua Hong , National Tsing Hua University, Taiwan
Cheng-Wen Wu , National Tsing Hua University, Taiwan
pp. 565
Session B7 (Special Session): Future of System Level Design Languages

SystemC Standard (Abstract)

Guido Arnout , CoWare, Inc., Santa Clara, CA
pp. 573

Java Based Object Oriented Hardware Specification and Synthesis (Abstract)

Tommy Kuhn , University of T?bingen, Germany
Wolfgang Rosenstiel , University of T?bingen and FZI, Germany
pp. 579

Superlog, a Unified Design Language for System-on-chip (Abstract)

Simon J. Davidmann , Co-Design Automation, Inc., San Jose, CA
Peter L. Flake , Co-Design Automation, Inc., San Jose, CA
pp. 583
Session C7: Delay Testing and Design-For-Testability

Performance Sensitivity Analysis Using Statistical Methods and Its Applications to Delay Testing (Abstract)

Jing-Jia Liou , University of California, Santa Barbara
Kwang-Ting Cheng , University of California, Santa Barbara
Sandip Kundu , Intel Corporation
Angela Krstic , University of California, Santa Barbara
Deb Aditya Mukherjee , Intel Corporation
pp. 587

A Testability Metric for Path Delay Faults and Its Application (Abstract)

Kwang-Ting Cheng , University of California, Santa Barbara
Huan-Chih Tsai , University of California, Santa Barbara
Vishwani D. Agrawal , Lucent Technologies, Murray Hill, NJ
pp. 593

A Non-Scan DFT Method at Register-Transfer Level to Achieve Complete Fault Efficiency (Abstract)

Hiroki Wada , Nara Institute of Science and Technology, Japan
Hideo Fujiwara , Nara Institute of Science and Technology, Japan
Toshimitsu Masuzawa , Nara Institute of Science and Technology, Japan
Satoshi Ohtake , Nara Institute of Science and Technology, Japan
pp. 599

A Sigma-Delta Modulation Based BIST Scheme for Mixed-Signal Circuits (Abstract)

Jiun-Lang Huang , University of California, Santa Barbara
Kwang-Ting Cheng , University of California, Santa Barbara
pp. 605
Session D7 (Panel Discussion): Industry-Academia Cooperation

null (PDF)

pp. null
Session E7: Signal Integrity / Noise Issues in Deep-Submicron

A 12b 50 MHz 3.3 V CMOS Acquisition Time Minimized A/D Converter (Abstract)

Young-Deuk Jeon , Sogang University, Seoul, Korea
Seung-Hoon Lee , Sogang University, Seoul, Korea
Seung-Chul Lee , Sogang University, Seoul, Korea
Byeong-Lyeol Jeon , Hyundai Electronics Industries Co., Ltd., Ichon, Korea
Sang-Min Yoo , Sogang University, Seoul, Korea
pp. 613

A Benchmark Suite for Substrate Analysis (Abstract)

Paolo Miliozzi , Conxant Systems Inc., Newport Beach, CA
Luis Miguel Silveira , Instituto de Engenharia de Sistemas e Computadores, Lisboa, Portual
Edoardo Charbon , Cadence Design Systems, San Jose, CA
pp. 617

Substrate Crosstalk Analysis in Mixed Signal CMOS Integrated Circuits (Abstract)

Makoto Nagata , Hiroshima University, Japan
Atsushi Iwata , Hiroshima University, Japan
pp. 623
Session A8: High Speed LSI Design for Entertainment Application

Importance of CAD Tools and Methodolgies in High Speed CPU Design (Abstract)

Nobuyuki Ikumi , Toshiba Corporation, Kawasaki, Japan
Masakazu Suzuoki , Sony Computer Entertainment Inc., Tokyo, Japan
Masato Nagamatsu , Toshiba Corporation, Kawasaki, Japan
Haruyuki Tago , Toshiba Corporation, Kawasaki, Japan
Yasuyuki Yamamoto , Sony Computer Entertainment Inc., Tokyo, Japan
Kazuhiro Hashimoto , Toshiba Corporation, Kawasaki, Japan
pp. 631

300MHz Design Methodology of VU for Emotion Synthesis (Abstract)

Toshinori Sato , TOSHIBA Corp., Japan
Hideki Takeda , TOSHIBA Corp., Japan
Yukio Endo , TOSHIBA Corp., Japan
Yukio Ootaguro , TOSHIBA Corp., Japan
Takayoshi Shimazawa , TOSHIBA Corp., Japan
Hiroaki Murakami , TOSHIBA Corp., Japan
Takayuki Kamei , TOSHIBA Corp., Japan
Kazuhiko Tachibana , TOSHIBA Corp., Japan
Fujio Ishihara , TOSHIBA Corp., Japan
Shin'ichi Kawakami , Toshiba Microelectoronics Corp., Japan
Nobuhiro Ide , TOSHIBA Corp., Japan
Akira Aono , Toshiba Microelectoronics Corp., Japan
Seiji Norimatsu , TOSHIBA Corp., Japan
Atsushi Kunimatsu , TOSHIBA Corp., Japan
pp. 635

Repeater Insertion Method and its Application to a 300MHz 128-bit 2-way Superscalar Microprocessor (Abstract)

Yukio Ohtaguro , Toshiba Corporation Semiconductor Company, Japan
Haruyuki Tago , Toshiba Corporation Semiconductor Company, Japan
Norman Kojima , Toshiba Corporation Semiconductor Company, Japan
Tatsuo Teruyama , Toshiba Corporation Semiconductor Company, Japan
Takayoshi Shimazawa , Toshiba Corporation Semiconductor Company, Japan
Masaaki Yamada , Toshiba Corporation Semiconductor Company, Japan
Hideki Takeda , Toshiba Corporation Semiconductor Company, Japan
Masataka Matsui , Toshiba Corporation Semiconductor Company, Japan
Kouji Hashizume , Toshiba Microelectronics Corp. Japan
Christian Klingner , Toshiba America Elec. Components, Inc., San Jose, CA
Yukiko Parameswar , Toshiba America Elec. Components, Inc., San Jose, CA
Shigeaki Iwasa , Toshiba Corporation Semiconductor Company, Japan
pp. 641

Clock Design of 300MHz 128-bit 2-way Superscalar Microprocessor (Abstract)

Ken-ichi Agawa , Toshiba Corporation, Japan
Fujio Ishihara , Toshiba Corporation, Japan
Christian Klingner , Toshiba America Elec. Components, Inc., San Jose, CA
pp. 647
Session B8 (Panel Discussion): One Language or More? (How Can We Design an SoC at a System Level?)
Session D8: High Performance Partitioning

Circuit Partitioning with Coupled Logic Restructuring Techniques (Abstract)

Xiao-Long Yuan , The Northwest Polytechnical University, China
Yu-Liang Wu , The Chinese University of HK, Shatin
David Ihsin Cheng , Ultima Interconnect Technology, Sunnyvale, CA
pp. 655

Improved Algorithms for Hypergraph Bipartitioning (Abstract)

Igor L. Markov , UCLA Computer Science Dept., Los Angeles, CA
Andrew E. Caldwell , UCLA Computer Science Dept., Los Angeles, CA
Andrew B. Kahng , UCLA Computer Science Dept., Los Angeles, CA
pp. 661

Multi-way Partitioning Using Bi-partition Heuristics (Abstract)

Jason Cong , UCLA, Los Angeles, CA
Majid Sarrafzadeh , Northwestern University, Evanston, IL
Maogang Wang , Northwestern University, Evanston, IL
Sung Kyu Lim , UCLA, Los Angeles, CA
pp. 667

Author's Index (PDF)

pp. 673
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