Organizing Committee (PDF)
Steering Committee (PDF)
General Chair's Message (PDF)
Technical Program Committee (PDF)
Technical Program Co-Chair's Message (PDF)
Best Paper Award Candidates (PDF)
University LSI Design Contest Committee (PDF)
University LSI Design Contest Co-Chair's Message (PDF)
University LSI Design Contest Summary (PDF)
University LSI Design Contest Awards (PDF)
Keynote Addresses (PDF)
EDA Vendor Executive Panel (PDF)
A VLSI Implementation of the Blowfish Encryption/Decryption Algorithm (PDF)
VLSI Implementation of Rake Receiver for IS-95 CDMA Testbed using FPGA (PDF)
VLSI Implementation of a Switch Fabric for Mixed ATM and IP Traffic (PDF)
Design of Digital Neural Cell Scheduler for Intelligent IB-ATM Switch (PDF)
Genetic Algorithm Accelerator GAA-II (PDF)
A Programmable Built-In Self-Test Core for Embedded Memories (PDF)
An Algorithm for VLSI Implementation of Highly Efficient Cubic-Polynomial Evaluation (PDF)
Design of Self-timed Asynchronous Booth's Multiplier (PDF)
High Speed and Ultra-Low Power 16X16 MAC Design using TG techniques for Web-based Multimedia System (PDF)
A Smart Imager for the Vision Processing Front-End (PDF)
A Binary Image Sensor with Flexible Motion Vector Detection using Block Matching Method (PDF)
An Arbitrary Chaos Generator Core Circuit Using PWM/PPM Signals (PDF)
An Application Specific Java Processor with Reconfigurabilities (PDF)
Reconfigurable Synchronized Dataflow Processor (PDF)
A 16-bit Redundant Binary Multiplier Using Low-Power Pass-Transistor Logic SPL (PDF)
An 8 x 8-b nRERL Serial Multiplier for Ultra-Low-Power Applications (PDF)
Essential Issues for IP Reuse (Abstract)
Usage-Based Characterization of Complex Functional Blocks for Reuse in Behavioral Synthesis (Abstract)
Reuse and Protection of Intellectual Property in the SpecC System (Abstract)
Fair Watermarking Techniques (Abstract)
Automatic Partitioning for Efficient Combinational Verification (Abstract)
A Hardware Simulation Engine Based on Decision Diagrams (Abstract)
Formal Verification based on Assume and Guarantee Approach - A Case Study (Abstract)
Multi-Clock Path Analysis Using Propositional Satisfiability (Abstract)
Self-Reforming Routing for Stochastic Search in VLSI Interconnection Layout (Abstract)
An Interconnect Topology Optimization by a Tree Transformation (Abstract)
Area Routing Oriented Hierarchical Corner Stitching with Partial Bin (Abstract)
Offline Program Re-mapping to Improve Branch Prediction Efficiency in Embedded Systems (Abstract)
Timing Driven Co-design of Networked Embedded Systems (Abstract)
Low-power Design Methodology and Applications utilizing Dual Supply Voltages (Abstract)
Co-synthesis with custom ASICs (Abstract)
A New Method for Constructing IP Level Power Model Based on Power Sensitivity (Abstract)
A Hybrid Approach for Core-Based System-Level Power Modeling (Abstract)
Synthesis of Low Power Folded Programmable Coefficient FIR Digital Filters (Abstract)
Synthesis Challenges for Next-Generation High-Performance and High-Density PLDs (Abstract)
KressArray Xplorer: A New CAD Environment to Optimize Reconfigurable Datapath Array Architectures (Abstract)
Hardware-Software Cosynthesis for Run-time Incrementally Reconfigurable FPGAs (Abstract)
A New Encoding Scheme for Rectangle Packing Problem (Abstract)
Analytical Minimization of Half-Perimeter Wirelength (Abstract)
Modeling and Minimization of Routing Congestion (Abstract)
System-In-Package (SIP): Challenges and Opportunities (Abstract)
Taiwan Foundry for System-In-Package (SIP) (Abstract)
Integration of Large-Scale FPGA and DRAM in a Package Using Chip-on-Chip Technology (Abstract)
Modeling and Analysis of Integrated Spiral Inductors for RF System-in-Package (Abstract)
Narrow Bus Encoding for Low Power Systems (Abstract)
Data Transmission Over a Bus with Peak-Limited Transition Activity (Abstract)
Power Analysis and Implementation of a Low-Power 300-MHz 8-b x 8-b Pipelined Multiplier (Abstract)
A New Approach to Assembly Software Retargeting for Microcontrollers (Abstract)
Register Allocation for Common Subexpressions in DSP Data Paths (Abstract)
A Technique for QoS-based System Partitioning (Abstract)
Exact Minimization of Fixed Polarity Reed-Muller Expressions for Incompletely Specified Functions (Abstract)
Three Parameters to Find Functional Decompositions (Abstract)
Delay-Optimal Wiring Plan for the Microprocessor of High Performance Computing Machines (Abstract)
MMP: A Novel Placement Algorithm for Combined Macro Block and Standard Cell Layout Design (Abstract)
Dynamic Weighting Monte Carlo for Constrained Floorplan Designs in Mixed Signal Application (Abstract)
Symbolic Circuit-Noise Analysis and Modeling with Determinant Decision Diagrams (Abstract)
Gate-Level Aged Timing Simulation Methodology for Hot-Carrier Reliability Assurance (Abstract)
Embedded Tutorial: IC Design Technology for Building System-On-A-Chip (PDF)
Thread Partitioning Method for Hardware Compiler Bach (Abstract)
An Area/Time Optimizing Algorithm in High-Level Synthesis for Control-Based Hardwares (Abstract)
A Timing-Driven Synthesis of Arithmetic Circuits using Carry-Save-Adders (Abstract)
Communicating Logic: An Alternative Embedded Stream Processing Paradigm (Abstract)
A Scheduling and Allocation Method to Reduce Data Transfer Time by Dynamic Reconfiguration (Abstract)
Power Reduction by Simultaneous Voltage Scaling and Gate Sizing (Abstract)
Analysis of Power-Clocked CMOS with Application to the Design of Energy-Recovery Circuits (Abstract)
Low-Power Design of Sequential Circuits Using a Quasi-Synchronous Derived Clock (Abstract)
FSM Decomposition by Direct Circuit Manipulation Applied to Low Power Design (Abstract)
Timing Closure: The Solution and Its Problems (Abstract)
High Performance of Short-Channel MOSFETs due to an Elevated Central-Channel Doping (Abstract)
Circuit Performance Oriented Device Optimization using BSIM3 Pre-Silicon Model Parameters (Abstract)
Design For Manufacturability: A Path From System Level To High Yielding Chips (PDF)
Low-Power Silicon Architecture for Wireless Communications (Abstract)
Run-time Power Control Scheme Using Software Feedback Loop for Low-Power Real-time Applications (Abstract)
An Interleaved Dual-Battery Power Supply for Battery-Operated Electronics (Abstract)
Embedded System Design with Multiple Languages (Abstract)
Symbolic Debugging of Globally Optimized Behavioral Specification (Abstract)
Fast Development of Source-level Debugging System Using Hardware Emulation (Abstract)
Methodology for Hardware/Software Co-verification in C/C++ (Abstract)
Performance-Optimal Clustering with Retiming for Sequential Circuits (Abstract)
IBAW: An Implication-Tree Based Alternative-Wiring Logic Transformation Algorithm (Abstract)
On Mixture Density and Maximum Likelihood Power Estimation via Expectation-Maximization (Abstract)
Edge Separability Based Circuit Clustering with Application to Circuit Partitioning (Abstract)
Feasible Two-Way Circuit Partitioning with Complex Resource Constraints (Abstract)
Performance Driven Multiway Partitioning (Abstract)
Hierarchical Computation of 3-D Interconnect Capacitance using Direct Boundary Element Method (Abstract)
An Analytic Calculation Method for Delay Time of RC-class Interconnects (Abstract)
Optimization of VDD and VTH for Low-Power and High-Speed Applications (Abstract)
Compact yet High-Performance (CyHP) Library for Short Time-to-Market with New Technologies (Abstract)
A New CMAC Neural Network Architecture and Its ASIC Realization (Abstract)
Retargetable Estimation Scheme for DSP Architecture Selection (Abstract)
Data Memory Minimization by Sharing Large Size Buffers (Abstract)
Array Allocation Taking into Account SDRAM Characteristics (Abstract)
Causality Based Generation Of Directed Test Cases (Abstract)
Fault Models and Test Generation for IDDQ Testing (Abstract)
Embedded Tutorial: Issues on SOC Testing in DSM Era (PDF)
A Cell Synthesis Method for Salicide Process (Abstract)
Monte-Carlo Algorithms for Layout Density Control (Abstract)
Layout Generation of Array Cell for NMOS 4-phase Dynamic Logic (Abstract)
A New Efficient Method for Substrate-Aware Device-Level Placement (Abstract)
Analog Testability Analysis by Determinant-Decision-Diagrams based Symbolic Analysis (Abstract)
A Method for Linking Process-level Varaiability to System Performances (Abstract)
Design Challenges for 0.1um and Beyond (Abstract)
Radix-4 Modular Multiplication and Exponentiation Algorithms for the RSA Public-Key Cryptosystem (Abstract)
Java Based Object Oriented Hardware Specification and Synthesis (Abstract)
Superlog, a Unified Design Language for System-on-chip (Abstract)
Performance Sensitivity Analysis Using Statistical Methods and Its Applications to Delay Testing (Abstract)
A Testability Metric for Path Delay Faults and Its Application (Abstract)
A Non-Scan DFT Method at Register-Transfer Level to Achieve Complete Fault Efficiency (Abstract)
A Sigma-Delta Modulation Based BIST Scheme for Mixed-Signal Circuits (Abstract)
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A 12b 50 MHz 3.3 V CMOS Acquisition Time Minimized A/D Converter (Abstract)
A Benchmark Suite for Substrate Analysis (Abstract)
Substrate Crosstalk Analysis in Mixed Signal CMOS Integrated Circuits (Abstract)
Importance of CAD Tools and Methodolgies in High Speed CPU Design (Abstract)
300MHz Design Methodology of VU for Emotion Synthesis (Abstract)
Repeater Insertion Method and its Application to a 300MHz 128-bit 2-way Superscalar Microprocessor (Abstract)
Clock Design of 300MHz 128-bit 2-way Superscalar Microprocessor (Abstract)
One Laguage or More? - How Can We Design an SoC at a System Level - (PDF)
Circuit Partitioning with Coupled Logic Restructuring Techniques (Abstract)
Improved Algorithms for Hypergraph Bipartitioning (Abstract)
Multi-way Partitioning Using Bi-partition Heuristics (Abstract)
Author's Index (PDF)