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Asia and South Pacific Design Automation Conference (2000)
Yokohama, Japan
Jan. 25, 2000 to Jan. 28, 2000
ISBN: 0-7803-5973-9
pp: 27
Hiroshi Sasaki , Tohoku University, Japan
Hitoshi Maruyama , Tohoku University, Japan
Hiroaki Kobayashi , Tohoku University, Japan
Tadao Nakamura , Tohoku University, Japan
Hideaki Tsukioka , Friendly Systems Co., Ltd., Japan
Nobuyoshi Shoji , Friendly Systems Co., Ltd., Japan
This paper describes the design and implementation of a reconfigurable synchronized dataflow processor (RSDP). The RSDP can configure its hardware to directly represent dataflow graphs (DFGs) of applications. Data are processed while they flow along application-specific datapaths in the RSDP. We have designed three DFGs for benchmarking and evaluated their performance on an RSDP board. The results show that the RSDP running at relatively lower frequency can achieve a competitive performance with a general-purpose processor.

H. Kobayashi, H. Sasaki, N. Shoji, T. Nakamura, H. Tsukioka and H. Maruyama, "Reconfigurable Synchronized Dataflow Processor," Asia and South Pacific Design Automation Conference(ASP-DAC), Yokohama, Japan, 2000, pp. 27.
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