The Community for Technology Leaders
Asia and South Pacific Design Automation Conference (1999)
Wanchai, Hong Kong
Jan. 18, 1999 to Jan. 21, 1999
ISBN: 0-7803-5012-X
TABLE OF CONTENTS
Session 1: Keynote Speech 1

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pp. null
Session 2A: Analog CAD

Symmetry Detection for Automatic Analog-Layout Recycling (Abstract)

C.-J. Richard Shi , University of Washington, Seattle
Youcef Bourai , University of Washington, Seattle
pp. 5

An SA-Based Nonlinear Function Synthesizer for Linear Analog Integrated Circuits (Abstract)

Runsheng Liu , Tsinghua Univ., Beijing, P.R. China
Huazhong Yang , Tsinghua Univ., Beijing, P.R. China
Hui Wang , Tsinghua Univ., Beijing, P.R. China
Rong Luo , Tsinghua Univ., Beijing, P.R. China
pp. 9
Session 2B: Physical Design 1 - Floorplanning

Relaxed Simulated Tempering for VLSI Floorplan Designs (Abstract)

Jason Cong , University of California, Los Angeles
Wing Hung Wong , University of California, Los Angeles
Jun S. Liu , University of California, Los Angeles
Tianming Kong , University of California, Los Angeles
Faming Liang , University of California, Los Angeles
Dongmin Xu , University of California, Los Angeles
pp. 13

Slicing Floorplans with Boundary Constraint (Abstract)

D. F. Wong , The University of Texas at Austin
F. Y. Young , The University of Texas at Austin
pp. 17

Design and Optimization of Power/Ground Network for Cell-Based VLSIs with Macro Cells (Abstract)

Xiaohai Wu , Tsinghua University, Beijing, China
Xianlong Hong , Tsinghua University, Beijing, China
Changge Qiao , Tsinghua University, Beijing, China
pp. 21
Session 2C: Design Contest

An 8b 52MHz Double-Channel CMOS A/D Converter for High-Speed Data Communications (Abstract)

Yong Jee , Sogang University, Seoul, Korea
Seung-Hoon Lee , Sogang University, Seoul, Korea
Sung-Wook Hwang , Hyundai Electronics Industries Co., Ltd., Ichon, Korea
Ju-Hyung Kim , Sogang University, Seoul, Korea
pp. 25

A 10b 50 MHz CMOS A/D Converter for High-Speed Video Applications (Abstract)

Byeong-Lyeol Jeon , Sogang University, Seoul, Korea
Sang-Won Yoon , Sogang University, Seoul, Korea
Kang-Jin Lee , Hyundai Electronics Industries Co., Ltd., Ichon, Korea
Seung-Hoon Lee , Sogang University, Seoul, Korea
pp. 29

The Design of Delay Insensitive Asynchronous 16-bit Microprocessor (Abstract)

Dong-Ik Lee , Kwang-Ju Institute of Science and Technology(K-JIST)
Dong-Wook Lee , Kwang-Ju Institute of Science and Technology(K-JIST)
Byung-Soo Choi , Kwang-Ju Institute of Science and Technology(K-JIST)
pp. 33

An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator Selection (Abstract)

Mutsuaki Goto , Hiroshima University, Japan
Yoshikatsu Nakayama , Hiroshima University, Japan
Koichi Hatta , Hiroshima University, Japan
Tetsushi Koide , Hiroshima University, Japan
Naoyoshi Toshine , Hiroshima University, Japan
Shin'ichi Wakabayashi , Hiroshima University, Japan
pp. 37

Motion Estimator LSI for MPEG2 High Level Standard (Abstract)

Chawalit Honsawek , Tokyo Institute of Technology, Tokyo
Shintaro Haba , Tokyo Institute of Technology, Tokyo
Li Jiang , Tokyo Institute of Technology, Tokyo
Hiroaki Kunieda , Tokyo Institute of Technology, Tokyo
Dongju Li , Tokyo Institute of Technology, Tokyo
pp. 41

A Single-Chip CMOS CCD Camera Interface Circuit with Digitally Controlled AGC (Abstract)

Jin-Kug Lee , Sogang University, Seoul, Korea
Seung-Hoon Lee , Sogang University, Seoul, Korea
Geun-Soon Kang , Samsung Electronics Co., Ltd., Yongin, Korea
Dong-Young Chang , Samsung Electronics Co., Ltd., Yongin, Korea
pp. 45

16-bit DSP and System for Baseband / Voiceband Processing of IS-136 Cellular Telephony (Abstract)

Tae Hun Kim , KAIST, Korea
Bae Sung Kwon , KAIST, Korea
Young Gon Kim , KAIST, Korea
Kyoo Hyun Lim , KAIST, Korea
Jeong Eun Lee , KAIST, Korea
Jeong Pyo Kim , KAIST, Korea
Jeongsik Yang , KAIST, Korea
Hyoung Sik Nam , KAIST, Korea
Sang Lin Byun , KAIST, Korea
Jin Wook Kim , KAIST, Korea
Beomsup Kim , KAIST, Korea
pp. 49
Session 3A: Circuit Simulation 1

Reduced-Order Modelling of Time-Varying Systems (Abstract)

Jaijeet Roychowdhury , Bell Laboratories, Murray Hill
pp. 53

Waveform Relaxation of Linear Integral-Differential Equations for Circuit Simulation (Abstract)

Omar Wing , The Chinese University of Hong Kong, P. R. China
Yao-Lin Jiang , Xi'an Jiaotong University, P. R. China
pp. 61

A New Technique to Exploit Frequency Domain Latency in Harmonic Balance Simulators (Abstract)

K. K. Gullapalli , Motorola, Austin, Texas
M. M. Zharov , IPPM, Russian Academy of Sciences, Moscow, Russia
B. J. Mulvaney , Motorola, Austin, Texas
M. M. Gourary , IPPM, Russian Academy of Sciences, Moscow, Russia
S. L. Ulyanov , IPPM, Russian Academy of Sciences, Moscow, Russia
S. G. Rusakov , IPPM, Russian Academy of Sciences, Moscow, Russia
pp. 65
Session 3B: Physical Design 2 - Partitioning

An Efficient Two-Level Partitioning Algorithm for VLSI Circuits (Abstract)

Jan-Ming Ho , Academia Sinica, Taipei, Taiwan
Sao-Jie Chen , National Taiwan Univ., Taipei
Chia-Chun Tsai , National Taiwan Univ., Taipei
Jong-Sheng Cherng , National Taiwan Univ., Taipei
pp. 69

A Clustering Based Linear Ordering Algorithm for K-Way Spectral Partitioning (Abstract)

TingTing Hwang , National Tsing Hua University, HsinChu, Taiwan
Shiuann-Shiuh Lin , National Tsing Hua University, HsinChu, Taiwan
Wen-Wei Lin , National Tsing Hua University, HsinChu, Taiwan
Wen-Hsin Chen , National Tsing Hua University, HsinChu, Taiwan
pp. 77

Faster and Better Spectral Algorithms for Multi-Way Partitioning (Abstract)

Yu-Chen Liu , Chung Yuan Christian University
Jan-Yang Chang , Chung Yuan Christian University
Ting-Chi Wang , Chung Yuan Christian University
pp. 81
Session 3C: EDA Roadmap

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pp. null
Session 4A: Circuit Simulation 2

VCO Jitter Simulation and Its Comparison With Measurement (Abstract)

Kenneth S. Kundert , Cadence Design Systems, San Jose, CA
Kimihiro Ogawa , Sony Corporation Semiconductor Company, Japan
Masayuki Takahashi , Sony Corporation Semiconductor Company, Japan
pp. 85

Enhancing the Efficiency of Reduction of Large RC networks By Pole Analysis via Congruence Transformations (Abstract)

Tian Lilin , Tsinghua University, Beijing, P R. China
Yang Zhilian , Tsinghua University, Beijing, P R. China
Zheng Hui , Tsinghua University, Beijing, P R. China
Zhang Wenjun , Tsinghua University, Beijing, P R. China
pp. 89

The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect Capacitance (Abstract)

Jinsong Hou , Tsinghua Univ., Beijing
Zeyi Wang , Tsinghua Univ., Beijing
Xianlong Hong , Tsinghua Univ., Beijing
pp. 93
Session 4B: Physical Design 3 - Interconnection

Interconnect Delay Estimation Models for Synthesis and Design Planning (Abstract)

Jason Cong , University of California, Los Angeles
David Zhigang Pan , University of California, Los Angeles
pp. 97

An Analytical Delay Model for SRAM-Based FPGA Interconnections (Abstract)

Tong Jiarong , Fudan University, Shanghai, China
Huang Zhijun , Fudan University, Shanghai, China
Tang Pushan , Fudan University, Shanghai, China
Zhou Feng , Fudan University, Shanghai, China
pp. 101

Timing-Driven Bipartitioning with Replication Using Iterative Quadratic Programming (Abstract)

Shihliang Ou , University of Southern California, Los Angeles
Massoud Pedram , University of Southern California, Los Angeles
pp. 105

An Integrated Battery-Hardware Model for Portable Electronics (Abstract)

Qing Wu , University of Southern California, Los Angeles
Chi-Ying Tsui , HK University of Science and Technology, Kowloon, Hong Kong
Massoud Pedram , University of Southern California, Los Angeles
pp. 109
Session 5A: Keynote Speech 2

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pp. null
Session 6A: Circuit 1 - Low-power/High-speed

Design Method of MTCMOS Power Switch for Low-Voltage High-Speed LSIs (Abstract)

Shinsuke Konaka , NTT Integrated Information & Energy System Laboratories, Japan
Shin-ichiro Mutoh , NTT Integrated Information & Energy System Laboratories, Japan
Satoshi Shigematsu , NTT Integrated Information & Energy System Laboratories, Japan
Yoshinori Gotoh , NTT Integrated Information & Energy System Laboratories, Japan
pp. 113

A New Single-Clock Flip-Clop for Half-Swing Clocking (Abstract)

Young-Su Kwon , KAIST, Korea
Bong-il Park , KAIST, Korea
In-Cheol Park , KAIST, Korea
Chong-Min Kyung , KAIST, Korea
pp. 117

Optimal Evaluation Clocking of Self-Resetting Domino Pipelines (Abstract)

Ayoob E. Dooply , University of California, San Diego
Kenneth Y. Yun , University of California, San Diego
pp. 121

Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion (Abstract)

Atsushi Takahashi , Tokyo Institute of Technology, Japan
Tomoyuki Yoda , Tokyo Institute of Technology, Japan
Yoji Kajitani , Tokyo Institute of Technology, Japan
pp. 125
Session 6B: Physical Design 4 - Analog, Noise

A Performance-Driven I/O Pin Routing Algorithm (Abstract)

Dongsheng Wang , University of California at San Diego
Chung-Kuan Cheng , University of California at San Diego
Arunabha Sen , University of California at San Diego
Ping Zhang , University of California at San Diego
pp. 129

An Automatic Router for the Pin Grid Array Package (Abstract)

Shuenn-Shi Chen , National Taiwan University, Taipei
Chia-Chun Tsai , National Taipei University of Technology, Taipei
Jong-Jang Chen , National Taiwan University, Taipei
Sao-Jie Chen , National Taiwan University, Taipei
pp. 133

Crosstalk Reduction by Transistor Sizing (Abstract)

Tong Xiao , University of California, Santa Barbara
Malgorzata Marek-Sadowska , University of California, Santa Barbara
pp. 137

A Technology-Independent Methodology of Placement Generation for Analog Circuit (Abstract)

Philip C. H. Chan , The Hone Kong University of Science and Technology
Wai-on Law , Motorola Semiconductors Hong Kong Ltd.
Wai-chee Wong , The Hone Kong University of Science and Technology
pp. 141
Session 6C: DA for Electronic Packages

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pp. null
Session 6D: Poster Session

Technnology Mapping for Low Power (Abstract)

Jinn-Shyan Wang , Nat'l Chung-Cheng Univ., Taiwan
Chin-Chao Chang , Nat'l Chung-Cheng Univ., Taiwan
Chingwei Yeh , Nat'l Chung-Cheng Univ., Taiwan
pp. 145

An Efficient Aopproach to Constrained Via Minimization for Two-Layer VLSI Routing (Abstract)

Maolin Tang , Edith Cowan University, Perth, Australia
Hon Nin Cheung , Edith Cowan University, Perth, Australia
Kamran Eshraghian , Edith Cowan University, Perth, Australia
pp. 149

Automatic Constraint Transformation with Integrated Parameter Space Exploration in Analog System Synthesis (Abstract)

Adrian Nunez-Aldana , University of Cincinnati, OH
Ranga Vemuri , University of Cincinnati, OH
Nagu R. Dhanwada , University of Cincinnati, OH
pp. 153

Node Sampling Technique to Speed Up Probability-Based Power Estimation Methods (Abstract)

Seung Ho Hwang , Korea Advanced Institute of Science and Technology, Taejon, Korea
Hoon Choi , Korea Advanced Institute of Science and Technology, Taejon, Korea
In-Cheol Park , Korea Advanced Institute of Science and Technology, Taejon, Korea
Chong-Min Kyung , Korea Advanced Institute of Science and Technology, Taejon, Korea
Hansoo Kim , Korea Advanced Institute of Science and Technology, Taejon, Korea
pp. 157

Acceleration of Linear Block Code Evaluations Using New Reconfigurable Computing Approach (Abstract)

Hidehisa Nagano , NTT Communication Science Laboratories, Japan
Takayuki Suyama , NTT Communication Science Laboratories, Japan
Akira Nagoya , NTT Communication Science Laboratories, Japan
pp. 161

A New Numerical Method for Transient Noise Analysis of Nonlinear Circuits (Abstract)

M. M. Zharov , IPPM, Russian Academy of Sciences, Moscow, Russia
B. J. Mulvaney , Motorola, Austin, Texas
S. L. Ulyanov , IPPM, Russian Academy of Sciences, Moscow, Russia
M. M. Gourary , IPPM, Russian Academy of Sciences, Moscow, Russia
S. G. Rusakov , IPPM, Russian Academy of Sciences, Moscow, Russia
pp. 165

Low Power CMOS Off-Chip Drivers with Slew-rate Difference (Abstract)

Rung-Bin Lin , Yuan-Ze University, Taiwan, R.O.C.
Jinq-Chang Chen , Yuan-Ze University, Taiwan, R.O.C.
pp. 169

Benchmark Circuits Improve the Quality of a Standard Cell Library (Abstract)

Isaac Shuo-Hsiu Chou , Yuan-Ze University, Taiwan
Rung-Bin Lin , Yuan-Ze University, Taiwan
Chi-Ming Tsai , Yuan-Ze University, Taiwan
pp. 173

Formal Design Verification for Correctness of Pipelined Microprocessors with Out-of-order Instruction Execution (Abstract)

Takashi Takenaka , Osaka University, Japan
Junji Kitamichi , Osaka University, Japan
Kenichi Taniguchi , Osaka University, Japan
Teruo Higashino , Osaka University, Japan
pp. 177

Solving the Rectangular Packing Problem by an Adaptive GA Based on Sequence-Pair (Abstract)

Koichi Hatta , Hiroshima University, Japan
Shin'ichi Wakabayashi , Hiroshima University, Japan
Tetsushi Koide , Hiroshima University, Japan
pp. 181

Hazard-Free Synthesis and Decomposition of Asynchronous Circuits (Abstract)

Ren-Der Chen , National Cheng Kung University, Tainan, Taiwan
Yeu-Horng Shiau , National Cheng Kung University, Tainan, Taiwan
Jer Min Jou , National Cheng Kung University, Tainan, Taiwan
pp. 185

Hierarchical Floorplan Design on the Internet (Abstract)

Jing-Yang Jou , National Chiao Tung University, Hsinchu, Taiwan
Hui-Ru Jiang , National Chiao Tung University, Hsinchu, Taiwan
Jiann-Horng Lin , National Chiao Tung University, Hsinchu, Taiwan
pp. 189

A Scheduling Method for Synchronous Communication in the Bach Hardware Compiler (Abstract)

Tetsuya Fujimoto , IC Group, Sharp Corporation, Japan
Akihisa Yamada , IC Group, Sharp Corporation, Japan
Takashi Kambe , IC Group, Sharp Corporation, Japan
Ryoji Sakurai , IC Group, Sharp Corporation, Japan
Andrew Kay , Sharp Laboratories of Europe, UK
Mizuki Takahashi , IC Group, Sharp Corporation, Japan
pp. 193
Session 7A: Circuit 2 - Multmedia chip designs

Electronics Development of Silicon Microdisplay for Virtual Reality Applications (Abstract)

H. C. Huang , The Hong Kong University of Science and Technology
P. W. Cheng , The Hong Kong University of Science and Technology
pp. 197

A Scalable Pipelined Architecture for Separable 2-D Discrete Wavelet Transform (Abstract)

Yeu-Horng Shiau , National Cheng Kung University, Taiwan
Jer Min Jou , National Cheng Kung University, Taiwan
Ming-Shiang Liang , National Cheng Kung University, Taiwan
Pei-Yin Chen , National Cheng Kung University, Taiwan
pp. 205

A New Pipelined Architecture for Fuzzy Color Correction (Abstract)

Jer Min Jou , National Cheng Kung University, Taiwan
Shiann-Rong Kuang , National Cheng Kung University, Taiwan
Yeu-Horng Shiau , National Cheng Kung University, Taiwan
pp. 209
Session 7B: Physical Design 5 - Special Topics

Watermarking Layout Topologies (Abstract)

Edoardo Charbon , Cadence Design Systems Inc., San Jose, California
Ilhami Torunoglu , Cadence Design Systems Inc., San Jose, California
pp. 213

Optimal Wire Shape with Consideration of Coupling Capacitance under Elmore Delay Model (Abstract)

D. F. Wong , University of Texas at Austin, Texas
Youxin Gao , University of Texas at Austin, Texas
pp. 217

New Multilevel and Hierarchical Algorithms for Layout Density Control (Abstract)

Alexander Zelikovsky , UCLA Department of Computer Science, Los Angeles, CA
Anish Singh , University of Virginia, Charlottesville, VA
Gabriel Robins , University of Virginia, Charlottesville, VA
Andrew B. Kahng , UCLA Department of Computer Science, Los Angeles, CA
pp. 221

Function Smoothing with Applications to VLSI Layout (Abstract)

Igor L. Markov , UCLA Mathematics Dept., Los Angeles
Ross Baldick , University of Texas, Austin
Andrew Kennings , Ryerson Polytechnic Univ., Toronto, ON
Andrew B. Kahng , UCLA CS Dept., Los Angeles
pp. 225
Session 7C: Panel - System-on-a-chip

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pp. null
Session 8A: Timing analysis

Layout-based Logic Decomposition for Timing Optimization (Abstract)

Yun-Yin Lian , National Tsing Hua University, Taiwan
Youn-Long Lin , National Tsing Hua University, Taiwan
pp. 229

Timing Optimization of Logic Network Using Gate Duplication (Abstract)

Chi-ying Tsui , The Hong Kong University of Science & Technology, Clear Water Bay
Chun-hong Chen , Zhejiang University of Technology, HangZhou
pp. 233

Model Order Reduction of Large Circuits Using Balanced Truncation (Abstract)

Massoud Pedram , University of Southern California, Los Angeles
Payam Rabiei , University of Southern California, Los Angeles
pp. 237
Session 8B: Physical Design 6 - Placement & Route

Optimization of Linear Placements for Wirelength Minimization with Free Sites (Abstract)

Alex Zelikovsky , UCLA CS Department, Los Angeles
Paul Tucker , UCSD CSE Department, La Jolla
Andrew B. Kahng , UCLA CS Department, Los Angeles
pp. 241

A New Global Routing Algorithm Independent Of Net Ordering (Abstract)

Haiyun Bao , Tsinghua Univ. Beijing, China
Xianlong Hong , Tsinghua Univ. Beijing, China
Yici Cai , Tsinghua Univ. Beijing, China
pp. 245

A Timing-Driven Block Placer Based on Sequence Pair Model (Abstract)

Gang Huang , Tsinghua University, Beijing, China
Changge Qiao , Tsinghua University, Beijing, China
Yici Cai , Tsinghua University, Beijing, China
Xianlong Hong , Tsinghua University, Beijing, China
pp. 249

Recent Advances in Asynchronous Design Methodologies (Abstract)

Kenneth Y. Yun , University of California, San Diego
pp. 253
Session 9: Keynote Speech 3

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pp. null
Session 10A: Circuit 3 - Analog & Mixed Circuit

Universal Switched-Current Integrator Blocks for SI Filter Design (Abstract)

Steve S. Chung , National Chiao Tung University, Taiwan
Jack L. Chan , National Chiao Tung University, Taiwan; AMIC Technology, Taiwan
pp. 261

An On-Chip Automatic Tuning Circuit using Integration Level Approximation (Abstract)

Jang Myung-Jun , LG Semicon Device, Korea
Lee Sung-Dae , Ansan Technical College, Korea
Leex Won-Hyo , SungKyunKwan Univ., Korea
pp. 265

A High Speed and Low Power Phase-Frequency Detector and Charge - pump (Abstract)

Sung - Dae Lee , Ansan Technical College, Korea
Won - Hyo Lee , Sungkyunkwan Univ., Korea
Jun - Dong Cho , Sungkyunkwan Univ., Korea
pp. 269

A Single-Chip CMOS CCD Camera Interface Circuit with Digitally Controlled AGC (Abstract)

Seung-Hoon Lee , Sogang University, Seoul, Korea
Dong-Young Chang , Samsung Electronics Co., Ltd., Yongin, Korea
Geun-Soon Kang , Samsung Electronics Co., Ltd., Yongin, Korea
Jin-Kug Lee , Sogang University, Seoul, Korea
pp. 273
Session 10B: Testing 1

Data Path Synthesis for BIST with Low Area Overhead (Abstract)

Xiaowei Li , The University of Hong Kong
Paul Y. S. Cheung , The University of Hong Kong
pp. 275

Testing Interconnects of Dynamic Reconfigurable FPGAs (Abstract)

Chi-Feng Wu , National Tsing Hua University, Hsinchu, Taiwan
Cheng-Wen Wu , National Tsing Hua University, Hsinchu, Taiwan
pp. 279

Diagnosing Single Faults for Interconnects in SRAM Based FPGAs (Abstract)

Fabrizio Lombardi , Northeastern University, Boston, MA
Yinlei Yu , Fudan University, Shanghai, China
Wei Kang Huang , Fudan University, Shanghai, China
Jian Xu , Fudan University, Shanghai, China
pp. 283

An Adaptive BIST to Detect Multiple Stuck-Open Faults in CMOS circuits (Abstract)

Debesh K. Das , Jadavpur University, Calcutta, India
Bhargab B. Bhattacharya , Indian Statistical Institute, Calcutta, India
Hafijur Rahaman , A. P. C. Roy Polytechnic, Calcutta, India
pp. 287
Session 11A: Power Estimation/Low-power

Estimation of Peak Current through CMOS VLSI Circuit Supply Lines (Abstract)

Haruhiko Yamaguchi , Sony Corporation Semiconductor Company, Japan
Kimihiro Ogawa , Sony Corporation Semiconductor Company, Japan
Toshio Murayama , Sony Corporation Semiconductor Company, Japan
pp. 295

Power Consumption in XOR-Based Circuits (Abstract)

Kaushik Roy , Purdue University, West Lafayette, IN
Rolf Drechsler , Albert-Ludwigs-University, Germany
Yibin Ye , Purdue University, West Lafayette, IN
pp. 299

Exploiting Don't Caers During Data Sequencing using Genetic Algorithms (Abstract)

Nicole Drechsler , Albert-Ludwigs-University, Germany
Rolf Drechsler , Albert-Ludwigs-University, Germany
pp. 303
Session 11B: Testing 2 - Testing and formal Verification

An Efficient Structural Approach to Board Interconnect Diagnosis (Abstract)

Philip C. H. Chan , The Hong Kong University of Science and Technology
Chun-Keung Lo , The Hong Kong University of Science and Technology
pp. 307

On the Testing Quality of Random and Pseudo-random Sequences for Permanent and Intermittent Faults (Abstract)

Jin Ding , Beijing Univ. of Posts & Telecom., China
Yu-Liang Wu , The Chinese University of Hong Kong, Shatin
pp. 311

Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits (Abstract)

Bernd Becker , Albert-Ludwigs-University, Germany
Nicole Drechsler , Albert-Ludwigs-University, Germany
Martin Keim , Albert-Ludwigs-University, Germany
pp. 315

Formal Verification Method for Combinatorial Circuits at High Level Design (Abstract)

Junji Kitamichi , Osaka University, Japan
Nobuo Funabiki , Osaka University, Japan
Hiroyuki Kageyama , Osaka University, Japan
pp. 319
Session 11C: Panel - VLSI Design Education

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pp. null
Session 12A: BDD

Minimization of Free BDDs (Abstract)

Wolfgang G?nther , Albert-Ludwigs-University, Germany
Rolg Drechsler , Albert-Ludwigs-University, Germany
pp. 323

Application Driven Variable Reordering and an Example Implementation in Reachability Analysis (Abstract)

Klaus Schwettmann , University of Trier, Germany
Christoph Meinel , TI, Bahnhofstr., Germany; University of Trier, Germany
Anna Slobodov? , TI, Bahnhofstr., Germany
pp. 327

Realization of Regular Ternary Logic Functions (Abstract)

Tsutomu Sasao , Kyushu Institute of Technology, Japan
Munehiro Matsuura , Kyushu Institute of Technology, Japan
Atsumu Iseno , Meiji University, Japan
Yukihiro Iguchi , Meiji University, Japan
pp. 331
Session 12B: Systems/HW SW co-design

A Hardware/Software Partitioning Algorithm for Processor Cores of Digital Signal Processing (Abstract)

Tatsuo Ohtsuki , Waseda University
Masao Yanagisawa , Waseda University
Nozomu Togawa , Waseda University
Takashi Sakurai , Waseda University
pp. 335

Generation of Interpretive and Compiled Instruction Set Simulators (Abstract)

Johann Elste , University of Dormund, Germany
Rainer Leupers , University of Dormund, Germany
Birger Landwehr , University of Dormund, Germany
pp. 339

Combining Speculative Execution and Conditional Resource Sharing to Efficiently Schedule Conditional Behaviors (Abstract)

Apostolos A. Kountouris , IRISA, Campus Universitaire de Beaulieu, France
Christophe Wolinski , IRISA, Campus Universitaire de Beaulieu, France
pp. 343

Fast Instruction Cache Simulation Strategies in a Hardware/Software Co-Design Environment (Abstract)

Alberto Sangiovanni-Vincentelli , University of California at Berkeley, CA
Luciano Lavagno , Politecnico di Torino, Italy
Marcello Lajolo , Politecnico di Torino, Italy
pp. 347
Session 12C: Behavioral/FPGA

A Multi-Level FPGA Synthesis Method Supporting HDL Debugging for Emulation-Based Designs (Abstract)

Wen-Jong Fang , Tsing Hua University, Taiwan
Allen C.-H. Wu , Tsing Hua University, Taiwan
Peng-Cheng Kao , Tsing Hua University, Taiwan
pp. 351

Fast Boolean Matching Under Permutation Using Representative (Abstract)

Tsutomu Sasao , Kyushu Institute of Technology, Japan
Debatosh Debnath , Kyushu Institute of Technology, Japan
pp. 359

FSM Modeling of Synchronous VHDL Design for Symbolic Model Checking (Abstract)

Hongxi Xue , Tsinghua University, Beijing, P.R. China
Xianlong Hong , Tsinghua University, Beijing, P.R. China
Hongxing Li , Tsinghua University, Beijing, P.R. China
Jinsong Bei , Tsinghua University, Beijing, P.R. China
Jinian Bian , Tsinghua University, Beijing, P.R. China
pp. 363
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