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Asia and South Pacific Design Automation Conference (1999)
Wanchai, Hong Kong
Jan. 18, 1999 to Jan. 21, 1999
ISBN: 0-7803-5012-X
pp: 149
Maolin Tang , Edith Cowan University, Perth, Australia
Kamran Eshraghian , Edith Cowan University, Perth, Australia
Hon Nin Cheung , Edith Cowan University, Perth, Australia
ABSTRACT
Constrained Via Minimization is the problem of reassigning wire segments of a VLSI routing so that the number of vias is minimized. In this paper, a new approach is proposed for two-layer VLSI routing. This approach is able to handle any types of routing, and allows arbitrary number of wire segments split at a via candidate.
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CITATION

M. Tang, H. N. Cheung and K. Eshraghian, "An Efficient Aopproach to Constrained Via Minimization for Two-Layer VLSI Routing," Asia and South Pacific Design Automation Conference(ASP-DAC), Wanchai, Hong Kong, 1999, pp. 149.
doi:10.1109/ASPDAC.1999.759982
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