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2017 IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP) (2017)
Seattle, WA, USA
July 10, 2017 to July 12, 2017
ISSN: 2160-052X
ISBN: 978-1-5090-4826-7
TABLE OF CONTENTS

[Front cover] (PDF)

pp. c1

A message from the general chair and program chair (PDF)

Ken Eguro , Microsoft Research, Redmond, WA, USA
Ryan Kastner , University of California, San Diego, United States of America
pp. 1

Keynotes (PDF)

pp. 1-2

Author index (PDF)

pp. 213-215

CATERPILLAR: Coarse Grain Reconfigurable Architecture for accelerating the training of Deep Neural Networks (Abstract)

Yuanfang Li , Stanford University, United States of America
Ardavan Pedram , Stanford University, United States of America
pp. 1-10

Fast and efficient implementation of Convolutional Neural Networks on FPGA (Abstract)

Abhinav Podili , Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, USA
Chi Zhang , Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, USA
Viktor Prasanna , Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, USA
pp. 11-18

Parallel Multi Channel convolution using General Matrix Multiplication (Abstract)

Aravind Vasudevan , School of Computer Science and Statistics, Trinity College Dublin, Republic of Ireland
Andrew Anderson , School of Computer Science and Statistics, Trinity College Dublin, Republic of Ireland
David Gregg , School of Computer Science and Statistics, Trinity College Dublin, Republic of Ireland
pp. 19-24

High-performance FPGA implementation of equivariant adaptive separation via independence algorithm for Independent Component Analysis (Abstract)

Mahdi Nazemi , Department of Electrical Engineering, University of Southern California, Los Angeles, USA
Shahin Nazarian , Department of Electrical Engineering, University of Southern California, Los Angeles, USA
Massoud Pedram , Department of Electrical Engineering, University of Southern California, Los Angeles, USA
pp. 25-28

Design and comparative evaluation of GPGPU- and FPGA-based MPSoC ECU architectures for secure, dependable, and real-time automotive CPS (Abstract)

Bikash Poudel , Department of Computer Science and Engineering, University of Nevada Reno, United States of America
Naresh Kumar Giri , Department of Computer Science, Kansas State University, United States of America
Arslan Munir , Department of Computer Science, Kansas State University, United States of America
pp. 29-36

High-Level Synthesis for side-channel defense (Abstract)

S. T. Choden Konigsmark , Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, United States of America
Deming Chen , Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, United States of America
Martin D. F. Wong , Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, United States of America
pp. 37-44

DoSGuard: Protecting pipelined MPSoCs against hardware Trojan based DoS attacks (Abstract)

Amin Malekpour , School of Computer Science and Engineering, University of New South Wales, Sydney, Australia
Roshan Ragel , Department of Computer Engineering, University of Peradeniya, Sri Lanka
Aleksandar Ignjatovic , School of Computer Science and Engineering, University of New South Wales, Sydney, Australia
Sri Parameswaran , School of Computer Science and Engineering, University of New South Wales, Sydney, Australia
pp. 45-52

Hardwiring the OS kernel into a Java application processor (Abstract)

Chun-Jen Tsai , Dept. of Computer Science, National Chiao Tung University, Hsinchu, Taiwan
Cheng-Ju Lin , Dept. of Computer Science, National Chiao Tung University, Hsinchu, Taiwan
Cheng-Yang Chen , Dept. of Computer Science, National Chiao Tung University, Hsinchu, Taiwan
Yan-Hung Lin , Dept. of Computer Science, National Chiao Tung University, Hsinchu, Taiwan
Wei-Jhong Ji , Dept. of Computer Science, National Chiao Tung University, Hsinchu, Taiwan
Sheng-Di Hong , Dept. of Computer Science, National Chiao Tung University, Hsinchu, Taiwan
pp. 53-60

Hardware support for embedded operating system security (Abstract)

Arman Pouraghily , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, USA
Tilman Wolf , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, USA
Russell Tessier , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, USA
pp. 61-66

Hardware-accelerated CCD readout smear correction for Fast Solar Polarimeter (Abstract)

Stefan Tabel , Semiconductor Laboratory of the Max Planck Society, Otto-Hahn-Ring 6, 81739 München, Germany
Korbinian Weikl , Semiconductor Laboratory of the Max Planck Society, Otto-Hahn-Ring 6, 81739 München, Germany
Walter Stechele , Integrated Systems, Technical University of Munich, Arcisstr. 21, 80290 München, Germany
pp. 67-74

Real-time object detection in software with custom vector instructions and algorithm changes (Abstract)

Joe Edwards , University of British Columbia, VectorBlox Computing Inc., Canada
Guy G.F. Lemieux , University of British Columbia, VectorBlox Computing Inc., Canada
pp. 75-82

An efficient embedded multi-ported memory architecture for next-generation FPGAs (Abstract)

S. Navid Shahrouzi , Department of Electrical and Computer Engineering, University of Colorado at Colorado Springs, USA
Darshika G. Perera , Department of Electrical and Computer Engineering, University of Colorado at Colorado Springs, USA
pp. 83-90

A Staged Memory Resource Management Method for CMP systems (Abstract)

Yangguo Liu , Microprocessor Research & Development Center, Peking University, Beijing, China
Junlin Lu , Microprocessor Research & Development Center, Peking University, Beijing, China
Dong Tong , Microprocessor Research & Development Center, Peking University, Beijing, China
Xu Cheng , Microprocessor Research & Development Center, Peking University, Beijing, China
pp. 91-98

CFStore: Boosting Hybrid storage performance by device crossfire (Abstract)

Wei Zhou , School of Computer Science and Technology, Wuhan National Laboratory for Optoelectronics, Huazhong University of Science and Technology, China
Dan Feng , School of Computer Science and Technology, Wuhan National Laboratory for Optoelectronics, Huazhong University of Science and Technology, China
Zhipeng Tan , School of Computer Science and Technology, Wuhan National Laboratory for Optoelectronics, Huazhong University of Science and Technology, China
pp. 99-106

RVNet: A fast and high energy efficiency network packet processing system on RISC-V (Abstract)

Yanpeng Wang , Department of Computer, National University of Defense Technology, Changsha, China 410073
Mei Wen , Department of Computer, National University of Defense Technology, Changsha, China 410073
Chunyuan Zhang , Department of Computer, National University of Defense Technology, Changsha, China 410073
Jie Lin , Department of Computer, National University of Defense Technology, Changsha, China 410073
pp. 107-110

Massive spatial query on the Kepler architecture (Abstract)

Yili Gong , State Key Laboratory of Software Engineering of China, School of Computer, Wuhan University, 430072, Hubei, China
Jia Tang , State Key Laboratory of Software Engineering of China, School of Computer, Wuhan University, 430072, Hubei, China
Wenhai Li , State Key Laboratory of Software Engineering of China, School of Computer, Wuhan University, 430072, Hubei, China
Zihui Ye , State Key Laboratory of Software Engineering of China, School of Computer, Wuhan University, 430072, Hubei, China
pp. 111-118

PFSI.sw: A programming framework for sea ice model algorithms based on Sunway many-core processor (Abstract)

Binyang Li , Department of Computer Science and Engineering, Sino-German Joint Software Institute, Beihang University, Beijing 100191, China
Bo Li , Department of Computer Science and Engineering, Sino-German Joint Software Institute, Beihang University, Beijing 100191, China
Depei Qian , Department of Computer Science and Engineering, Sino-German Joint Software Institute, Beihang University, Beijing 100191, China
pp. 119-126

MicRun: A framework for scale-free graph algorithms on SIMD architecture of the Xeon Phi (Abstract)

Jie Lin , College of Computer, National University of Defense Technology, Changsha, China
Qingbo Wu , College of Computer, National University of Defense Technology, Changsha, China
Yusong Tan , College of Computer, National University of Defense Technology, Changsha, China
Jie Yu , College of Computer, National University of Defense Technology, Changsha, China
Qi Zhang , College of Computer, National University of Defense Technology, Changsha, China
Xiaoling Li , College of Computer, National University of Defense Technology, Changsha, China
Lei Luo , College of Computer, National University of Defense Technology, Changsha, China
pp. 127-136

Hierarchical Dataflow Model for efficient programming of clustered manycore processors (Abstract)

Julien Hascoet , Kalray, Montbonnot-Saint-Martin, France
Karol Desnos , IETR, INSA Rennes, CNRS UMR 6164, UBL, France
Jean-Francois Nezan , IETR, INSA Rennes, CNRS UMR 6164, UBL, France
Benoit Dupont de Dinechin , Kalray, Montbonnot-Saint-Martin, France
pp. 137-142

Modeling and evaluation for gather/scatter operations in Vector-SIMD architectures (Abstract)

Hongbing Tan , National University of Defense Technology, Deya Road 109, Kaifu Street, Changsha, China
Haiyan Chen , National University of Defense Technology, Deya Road 109, Kaifu Street, Changsha, China
Sheng Liu , National University of Defense Technology, Deya Road 109, Kaifu Street, Changsha, China
Jianguo Wu , National University of Defense Technology, Deya Road 109, Kaifu Street, Changsha, China
pp. 143-148

reMinMin: A novel static energy-centric list scheduling approach based on real measurements (Abstract)

Achim Losch , Paderborn University, Germany
Marco Platzner , Paderborn University, Germany
pp. 149-154

Hardware design and analysis of efficient loop coarsening and border handling for image processing (Abstract)

M. Akif Ozkan , Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander University Erlangen-Nürnberg (FAU), Germany
Oliver Reiche , Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander University Erlangen-Nürnberg (FAU), Germany
Frank Hannig , Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander University Erlangen-Nürnberg (FAU), Germany
Jurgen Teich , Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander University Erlangen-Nürnberg (FAU), Germany
pp. 155-163

High performance hardware architectures for Intra Block Copy and Palette Coding for HEVC screen content coding extension (Abstract)

Rishan Senanayake , Paraqum Technologies, Dehiwala, Sri Lanka
Namitha Liyanage , Paraqum Technologies, Dehiwala, Sri Lanka
Sasindu Wijeratne , Paraqum Technologies, Dehiwala, Sri Lanka
Sachille Atapattu , Paraqum Technologies, Dehiwala, Sri Lanka
Kasun Athukorala , Paraqum Technologies, Dehiwala, Sri Lanka
P.M.K. Tharaka , Paraqum Technologies, Dehiwala, Sri Lanka
Geethan Karunaratne , Paraqum Technologies, Dehiwala, Sri Lanka
R.M.A.U. Senarath , Paraqum Technologies, Dehiwala, Sri Lanka
Ishantha Perera , Paraqum Technologies, Dehiwala, Sri Lanka
Ashen Ekanayake , Paraqum Technologies, Dehiwala, Sri Lanka
Ajith Pasqual , University of Moratuwa, Sri Lanka
pp. 164-169

Design and implementation of adaptive signal processing systems using Markov decision processes (Abstract)

Lin Li , University of Maryland, College Park, ECE Department, 20742, USA
Adrian E. Sapio , University of Maryland, College Park, ECE Department, 20742, USA
Jiahao Wu , University of Maryland, College Park, ECE Department, 20742, USA
Yanzhou Liu , University of Maryland, College Park, ECE Department, 20742, USA
Kyunghun Lee , University of Maryland, College Park, ECE Department, 20742, USA
Marilyn Wolf , Georgia Institute of Technology, USA
Shuvra S. Bhattacharyya , University of Maryland, College Park, ECE Department, 20742, USA
pp. 170-175

An embedded scalable linear model predictive hardware-based controller using ADMM (Abstract)

Pei Zhang , Electrical and Computer Engineering, Iowa State University, Ames, USA
Joseph Zambreno , Electrical and Computer Engineering, Iowa State University, Ames, USA
Phillip H. Jones , Electrical and Computer Engineering, Iowa State University, Ames, USA
pp. 176-183

CGRA-ME: A unified framework for CGRA modelling and exploration (Abstract)

S. Alexander Chin , Dept. of Electrical and Computer Engineering, University of Toronto, Canada
Noriaki Sakamoto , Dept. of Information and Communications Engineering, Tokyo Institute of Technology, Japan
Allan Rui , Dept. of Electrical and Computer Engineering, University of Toronto, Canada
Jim Zhao , Dept. of Electrical and Computer Engineering, University of Toronto, Canada
Jin Hee Kim , Dept. of Electrical and Computer Engineering, University of Toronto, Canada
Yuko Hara-Azumi , Dept. of Information and Communications Engineering, Tokyo Institute of Technology, Japan
Jason Anderson , Dept. of Electrical and Computer Engineering, University of Toronto, Canada
pp. 184-189

OpenCL-based design pattern for line rate packet processing (Abstract)

Jehandad Khan , NSF Center for High-Performance Reconfigurable Computing (CHREC), Virginia Tech, Blacksburg, United States of America
Peter Athanas , NSF Center for High-Performance Reconfigurable Computing (CHREC), Virginia Tech, Blacksburg, United States of America
Skip Booth , Cisco Systems Inc., RTP, North Carolina, United States of America
John Marshall , Cisco Systems Inc., RTP, North Carolina, United States of America
pp. 190-194

Acceleration of Frequent Itemset Mining on FPGA using SDAccel and Vivado HLS (Abstract)

Vinh Dang , Department of Computer Science, University of Virginia, Charlottesville, 22904, USA
Kevin Skadron , Department of Computer Science, University of Virginia, Charlottesville, 22904, USA
pp. 195-200

OpenMP device offloading to FPGA accelerators (Abstract)

Lukas Sommer , Embedded Systems and Applications Group, TU Darmstadt, Germany
Jens Korinth , Computer Systems Group, TU Darmstadt, Germany
Andreas Koch , Embedded Systems and Applications Group, TU Darmstadt, Germany
pp. 201-205

DeepPump: Multi-pumping deep Neural Networks (Abstract)

Ruizhe Zhao , Department of Computing, Imperial College London, United Kingdom
Tim Todman , Department of Computing, Imperial College London, United Kingdom
Wayne Luk , Department of Computing, Imperial College London, United Kingdom
Xinyu Niu , Department of Computing, Imperial College London, United Kingdom
pp. 206

Efficiency in ILP processing by using orthogonality (Abstract)

Marcel Brand , Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander University Erlangen-Nürnberg (FAU), Germany
Frank Hannig , Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander University Erlangen-Nürnberg (FAU), Germany
Alexandru Tanase , Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander University Erlangen-Nürnberg (FAU), Germany
Jurgen Teich , Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander University Erlangen-Nürnberg (FAU), Germany
pp. 207

A fast and accurate logarithm accelerator for scientific applications (Abstract)

Jing Chen , School of Computer Science, McGill University, Canada
Xue Liu , School of Computer Science, McGill University, Canada
pp. 208

Model checking cloud rendering system for the QoS evaluation (Abstract)

Haoyu Liu , School of Computer Engineering and Science, Shanghai University, 200444, China
Huahu Xu , School of Computer Engineering and Science, Shanghai University, 200444, China
Honghao Gao , School of Computer Engineering and Science, Shanghai University, 200444, China
Danqi Chu , Equipment Office, Shanghai University, 200444, China
pp. 209

High-throughput area-efficient processor for 3GPP LTE cryptographic core algorithms (Abstract)

Yuanhong Huo , School of Computer Science and Technology, Beijing Institute of Technology, China
Dake Liu , School of Information and Electronics, Beijing Institute of Technology, China
pp. 210

KV-FTL: A novel key-value based FTL scheme for large scale SSDs (Abstract)

Juan Li , State Key Laboratory of High Performance Computing, National University of Defense Technology, Changsha, China
Zhengguo Chen , State Key Laboratory of High Performance Computing, National University of Defense Technology, Changsha, China
Zhiguang Chen , State Key Laboratory of High Performance Computing, National University of Defense Technology, Changsha, China
Nong Xiao , State Key Laboratory of High Performance Computing, National University of Defense Technology, Changsha, China
Fang Liu , State Key Laboratory of High Performance Computing, National University of Defense Technology, Changsha, China
pp. 211
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