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2016 IEEE 27th International Conference on Application-specific Systems, Architectures and Processors (ASAP) (2016)
London, United Kingdom
July 6, 2016 to July 8, 2016
ISSN: 2160-052X
ISBN: 978-1-5090-1504-7
pp: 50-57
Sebastian Haas , Vodafone Chair Mobile Communications Systems, Center for Advancing Electronics Dresden (cfaed), Technische Universität, Germany
Tomas Karnagel , Database Technology Group, Center for Advancing Electronics Dresden (cfaed), Technische Universität, Germany
Oliver Arnold , Vodafone Chair Mobile Communications Systems, Center for Advancing Electronics Dresden (cfaed), Technische Universität, Germany
Erik Laux , Vodafone Chair Mobile Communications Systems, Center for Advancing Electronics Dresden (cfaed), Technische Universität, Germany
Benjamin Schlegel , Database Technology Group, Center for Advancing Electronics Dresden (cfaed), Technische Universität, Germany
Gerhard Fettweis , Vodafone Chair Mobile Communications Systems, Center for Advancing Electronics Dresden (cfaed), Technische Universität, Germany
Wolfgang Lehner , Database Technology Group, Center for Advancing Electronics Dresden (cfaed), Technische Universität, Germany
ABSTRACT
Compressed bitmap indices are heavily used in scientific and commercial database systems because they largely improve query performance for various workloads. Early research focused on finding tailor-made index compression schemes that are amenable for modern processors. Improving performance further typically comes at the expense of a lower compression rate, which is in many applications not acceptable because of memory limitations. Alternatively, tailor-made hardware allows to achieve a performance that can only hardly be reached with software running on general-purpose CPUs. In this paper, we will show how to create a custom instruction set framework for compressed bitmap processing that is generic enough to implement most of the major compressed bitmap indices. For evaluation, we implemented WAH, PLWAH, and COMPAX operations using our framework and compared the resulting implementation to multiple state-of-the-art processors. We show that the custom-made bitmap processor achieves speedups of up to one order of magnitude by also using two orders of magnitude less energy compared to a modern energy-efficient Intel processor. Finally, we discuss how to embed our processor with database-specific instruction sets into database system environments.
INDEX TERMS
Hardware, Instruction sets, Indexes, Encoding, Radiation detectors
CITATION

S. Haas et al., "HW/SW-database-codesign for compressed bitmap index processing," 2016 IEEE 27th International Conference on Application-specific Systems, Architectures and Processors (ASAP), London, United Kingdom, 2016, pp. 50-57.
doi:10.1109/ASAP.2016.7760772
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