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2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP) (2015)
Toronto, ON, Canada
July 27, 2015 to July 29, 2015
ISSN: 2160-052X
ISBN: 978-1-4799-1924-6
TABLE OF CONTENTS

Cover page (PDF)

pp. c1

Message from the ASAP 2015 chairs (PDF)

Jason Anderson , University of Toronto, Canada
Hayden Kwok-Hay So , The University of Hong Kong, Hong Kong
Deshanand Singh , Altera Corporation, Canada
pp. 1-2

Session list (PDF)

pp. 1

Program (PDF)

pp. 1-3

Automatic design of domain-specific instructions for low-power processors (Abstract)

Cecilia Gonzalez-Alvarez , ELIS department, Ghent University, Belgium
Jennifer B. Sartor , ELIS department, Ghent University, Belgium
Carlos Alvarez , DAC department, UPC - Barcelona Tech, Spain
Daniel Jimenez-Gonzalez , DAC department, UPC - Barcelona Tech, Spain
Lieven Eeckhout , ELIS department, Ghent University, Belgium
pp. 1-8

Custom FPGA-based soft-processors for sparse graph acceleration (Abstract)

Nachiket Kapre , School of Computer Engineering, Nanyang Technological University, Singapore
pp. 9-16

A soft-core processor array for relational operators (Abstract)

Raphael Polig , IBM Research - Zurich, Rueschlikon, Switzerland
Heiner Giefers , IBM Research - Zurich, Rueschlikon, Switzerland
Walter Stechele , Lehrstuhl für integrierte Systeme, Technische Universität München, Munich, Germany
pp. 17-24

Atomic stream computation unit based on micro-thread level parallelism (Abstract)

Nasim Farahini , Electronics and Embedded Systems Group, School of ICT, KTH, Sweden
Ahmed Hemani , Electronics and Embedded Systems Group, School of ICT, KTH, Sweden
pp. 25-29

Timing speculation-aware instruction set extension for resource-constrained embedded systems (Abstract)

Tanvir Ahmed , Dept. of Communications & Computer Engineering, Tokyo Institute of Technology, Japan
Yuko Hara-Azumi , Dept. of Communications & Computer Engineering, Tokyo Institute of Technology, Japan
pp. 30-34

A GPU-based correlator X-engine implemented on the CHIME Pathfinder (Abstract)

Nolan Denman , Dunlap Institute, University of Toronto, Canada
Mandana Amiri , Department of Physics and Astronomy, University of British Columbia, Canada
Kevin Bandura , Department of Physics, McGill University, Canada
Liam Connor , Dunlap Institute, University of Toronto, Canada
Matt Dobbs , Department of Physics, McGill University, Canada
Mateus Fandino , Department of Physics and Astronomy, University of British Columbia, Canada
Mark Halpern , Department of Physics and Astronomy, University of British Columbia, Canada
Adam Hincks , Department of Physics and Astronomy, University of British Columbia, Canada
Gary Hinshaw , Department of Physics and Astronomy, University of British Columbia, Canada
Carolin Hofer , Department of Physics and Astronomy, University of British Columbia, Canada
Peter Klages , Dunlap Institute, University of Toronto, Canada
Kiyoshi Masui , Department of Physics and Astronomy, University of British Columbia, Canada
Juan Mena Parra , Department of Physics, McGill University, Canada
Laura Newburgh , Dunlap Institute, University of Toronto, Canada
Andre Recnik , Dunlap Institute, University of Toronto, Canada
J. Richard Shaw , Canadian Institute for Theoretical Astrophysics, Canada
Kris Sigurdson , Department of Physics and Astronomy, University of British Columbia, Canada
Kendrick Smith , Perimeter Institute for Theoretical Physics, Canada
Keith Vanderlinde , Dunlap Institute, University of Toronto, Canada
pp. 35-40

Power and performance trade-offs for Space Time Adaptive Processing (Abstract)

Nitin A. Gawande , Pacific Northwest National Laboratory, Richland, WA, USA
Joseph B. Manzano , Pacific Northwest National Laboratory, Richland, WA, USA
Antonino Tumeo , Pacific Northwest National Laboratory, Richland, WA, USA
Nathan R. Tallent , Pacific Northwest National Laboratory, Richland, WA, USA
Darren J. Kerbyson , Pacific Northwest National Laboratory, Richland, WA, USA
Adolfy Hoisie , Pacific Northwest National Laboratory, Richland, WA, USA
pp. 41-48

Accelerating persistent scatterer pixel selection for InSAR processing (Abstract)

Tahsin Reza , Electrical and Computer Engineering, University of British Columbia, Canada
Aaron Zimmer , 3vGeomatics, Vancouver, Canada
Parwant Ghuman , 3vGeomatics, Vancouver, Canada
Tanuj kr Aasawat , Electrical and Computer Engineering, University of British Columbia, Canada
Matei Ripeanu , Electrical and Computer Engineering, University of British Columbia, Canada
pp. 49-56

An efficient real-time data pipeline for the CHIME Pathfinder radio telescope X-engine (Abstract)

Andre Recnik , Dunlap Institute for Astronomy & Astrophysics, University of Toronto, Canada
Kevin Bandura , Department of Physics, McGill University, Canada
Nolan Denman , Dunlap Institute for Astronomy & Astrophysics, University of Toronto, Canada
Adam D. Hincks , Department of Physics and Astronomy, University of British Columbia, Canada
Gary Hinshaw , Department of Physics and Astronomy, University of British Columbia, Canada
Peter Klages , Dunlap Institute for Astronomy & Astrophysics, University of Toronto, Canada
Ue-Li Pen , Canadian Institute for Theoretical Astrophysics, University of Toronto, Canada
Keith Vanderlinde , Dunlap Institute for Astronomy & Astrophysics, University of Toronto, Canada
pp. 57-61

An IEEE 754 double-precision floating-point multiplier for denormalized and normalized floating-point numbers (Abstract)

Ross Thompson , Air Force Research Laboratory, 525 Brooks Road, Rome, NY 13441 USA
James E. Stine , Oklahoma State University, VLSI Computer Architecture Research Group, Department of Electrical and Computer Engineering, Stillwater, 74078 USA
pp. 62-63

Dual-rail active protection system against side-channel analysis in FPGAs (Abstract)

Wei He , Lab of Physical Analysis and Cryptographic Engineering, Nanyang Technological University, Singapore, 637371
Dirmanto Jap , School of Physical and Mathematical Sciences, Nanyang Technological University, Singapore, 637371
pp. 64-65

Does arithmetic logic dominate data movement? a systematic comparison of energy-efficiency for FFT accelerators (Abstract)

Tung Thanh-Hoang , Department of Computer Science, University of Chicago, Illinois, USA
Amirali Shambayati , Department of Computer Science, University of Chicago, Illinois, USA
Henry Hoffmann , Department of Computer Science, University of Chicago, Illinois, USA
Andrew A. Chien , Department of Computer Science, University of Chicago, Illinois, USA
pp. 66-67

An FPGA implementation of a Restricted Boltzmann Machine classifier using stochastic bit streams (Abstract)

Bingzhe Li , Department of Electrical and Computer Engineering, University of Minnesota-Twin Cities, Minneapolis, USA, 55455
M. Hassan Najafi , Department of Electrical and Computer Engineering, University of Minnesota-Twin Cities, Minneapolis, USA, 55455
David J. Lilja , Department of Electrical and Computer Engineering, University of Minnesota-Twin Cities, Minneapolis, USA, 55455
pp. 68-69

Application-set driven exploration for custom processor architectures (Abstract)

Mehmet Ali Arslan , Department of Computer Science, Lund University, Sweden
Flavius Gruian , Department of Computer Science, Lund University, Sweden
Krzysztof Kuchcinski , Department of Computer Science, Lund University, Sweden
pp. 70-71

Speeding up graph-based SLAM algorithm: A GPU-based heterogeneous architecture study (Abstract)

Abdelhamid Dine , Institut d'Electronique Fondamentale. Université Paris-Sud, 91405, Orsay, FRANCE
Abdelhafid Elouardi , Institut d'Electronique Fondamentale. Université Paris-Sud, 91405, Orsay, FRANCE
Bastien Vincke , Institut d'Electronique Fondamentale. Université Paris-Sud, 91405, Orsay, FRANCE
Samir Bouaziz , Institut d'Electronique Fondamentale. Université Paris-Sud, 91405, Orsay, FRANCE
pp. 72-73

Range reduction based on Pythagorean triples for trigonometric function evaluation (Abstract)

Hugues de Lassus Saint-Genies , Univ. Perpignan Via Domitia, DALI, F-66860, France
David Defour , Univ. Perpignan Via Domitia, DALI, F-66860, France
Guillaume Revy , Univ. Perpignan Via Domitia, DALI, F-66860, France
pp. 74-81

LightSpMV: Faster CSR-based sparse matrix-vector multiplication on CUDA-enabled GPUs (Abstract)

Yongchao Liu , School of Computational Science & Engineering, Georgia Institute of Technology, Atlanta, 30332, USA
Bertil Schmidt , Institut für Informatik, Johannes Gutenberg Universität Mainz, 55128, Germany
pp. 82-89

GPU-based multifrontal optimizing method in sparse Cholesky factorization (Abstract)

Ran Zheng , Services Computing Technology and System Lab, Cluster and Grid Computing Lab, School of Computer Science and Technology, Huazhong University of Science and Technology, Wuhan, 430074, China
Wei Wang , Services Computing Technology and System Lab, Cluster and Grid Computing Lab, School of Computer Science and Technology, Huazhong University of Science and Technology, Wuhan, 430074, China
Hai Jin , Services Computing Technology and System Lab, Cluster and Grid Computing Lab, School of Computer Science and Technology, Huazhong University of Science and Technology, Wuhan, 430074, China
Song Wu , Services Computing Technology and System Lab, Cluster and Grid Computing Lab, School of Computer Science and Technology, Huazhong University of Science and Technology, Wuhan, 430074, China
Yong Chen , Services Computing Technology and System Lab, Cluster and Grid Computing Lab, School of Computer Science and Technology, Huazhong University of Science and Technology, Wuhan, 430074, China
Han Jiang , Department of Power System, China Electric Power Research Institute, Beijing, 100085, China
pp. 90-97

A metamorphotic Network-on-Chip for various types of parallel applications (Abstract)

Seiichi Tade , Keio University, 3-14-1 Hiyoshi, Kohoku-ku, Yokohama, Japan
Hiroki Matsutani , Keio University, 3-14-1 Hiyoshi, Kohoku-ku, Yokohama, Japan
Hideharu Amano , Keio University, 3-14-1 Hiyoshi, Kohoku-ku, Yokohama, Japan
Michihiro Koibuchi , National Institute of Informatics, 2-1-2 Hitotsubashi, Chiyoda-ku, Tokyo, Japan
pp. 98-105

Dynamic pipeline-partitioned video decoding on symmetric stream multiprocessors (Abstract)

Ming-Ju Wu , Department of Computer Science, National Chiao Tung University, Hsinchu, Taiwan
Yan-Ting Chen , Department of Computer Science, National Chiao Tung University, Hsinchu, Taiwan
Chun-Jen Tsai , Department of Computer Science, National Chiao Tung University, Hsinchu, Taiwan
pp. 106-110

Stochastic circuit design and performance evaluation of vector quantization (Abstract)

Ran Wang , Department of Electrical and Computer Engineering, University of Alberta, Edmonton, T6G 2V4, Canada
Jie Han , Department of Electrical and Computer Engineering, University of Alberta, Edmonton, T6G 2V4, Canada
Bruce Cockburn , Department of Electrical and Computer Engineering, University of Alberta, Edmonton, T6G 2V4, Canada
Duncan Elliott , Department of Electrical and Computer Engineering, University of Alberta, Edmonton, T6G 2V4, Canada
pp. 111-115

Mixed-signal implementation of differential decoding using binary message passing algorithms (Abstract)

Glenn Cowan , Department of ECE, Concordia University, Montreal, Canada
Kevin Cushon , Microtechnology and Nanoscience, Chalmers University of Technology, Gothenburg, Sweden
Warren Gross , Department of ECE, McGill University, Montreal, Canada
pp. 116-119

Hardware acceleration of Private Information Retrieval protocols using GPUs (Abstract)

Mihai Maruseac , UMass Boston, USA
Gabriel Ghinita , UMass Boston, USA
Ming Ouyang , UMass Boston, USA
Razvan Rughinis , Politehnica University, Romania
pp. 120-127

Accelerating bootstrapping in FHEW using GPUs (Abstract)

Moon Sung Lee , Dept. of Mathematical Sciences, Seoul National University, Korea
Yongje Lee , Dept. of Electrical and Computer Engineering and Inter-University Semiconductor Research Center (ISRC), Seoul National University, Korea
Jung Hee Cheon , Dept. of Mathematical Sciences, Seoul National University, Korea
Yunheung Paek , Dept. of Electrical and Computer Engineering and Inter-University Semiconductor Research Center (ISRC), Seoul National University, Korea
pp. 128-135

Multi-task support for security-enabled embedded processors (Abstract)

Tedy Thomas , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, USA
Arman Pouraghily , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, USA
Kekai Hu , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, USA
Russell Tessier , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, USA
Tilman Wolf , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, USA
pp. 136-143

Towards secure cryptographic software implementation against side-channel power analysis attacks (Abstract)

Pei Luo , Electrical & Computer Engineering Department, Northeastern University, Boston, MA 02115 USA
Liwei Zhang , Department of Mathematics, Northeastern University, Boston, MA 02115 USA
Yunsi Fei , Electrical & Computer Engineering Department, Northeastern University, Boston, MA 02115 USA
A. Adam Ding , Department of Mathematics, Northeastern University, Boston, MA 02115 USA
pp. 144-148

Programmable RNS lattice-based parallel cryptographic decryption (Abstract)

Paulo Martins , INESC-ID, Instituto Superior Técnico, Universidade de Lisboa, Rua Alves Redol, 9, 1000-029, Portugal
Leonel Sousa , INESC-ID, Instituto Superior Técnico, Universidade de Lisboa, Rua Alves Redol, 9, 1000-029, Portugal
Julien Eynard , Sorbonne Universités, UPMC Univ Paris 06, CNRS, LIP6 UMR 7606, 4 place Jussieu 75005, France
Jean-Claude Bajard , Sorbonne Universités, UPMC Univ Paris 06, CNRS, LIP6 UMR 7606, 4 place Jussieu 75005, France
pp. 149-153

Balance power leakage to fight against side-channel analysis at gate level in FPGAs (Abstract)

Xin Fang , Electrical & Computer Engineering Department, Northeastern University, Boston, MA 02115 USA
Pei Luo , Electrical & Computer Engineering Department, Northeastern University, Boston, MA 02115 USA
Yunsi Fei , Electrical & Computer Engineering Department, Northeastern University, Boston, MA 02115 USA
Miriam Leeser , Electrical & Computer Engineering Department, Northeastern University, Boston, MA 02115 USA
pp. 154-155

How can Garbage Collection be energy efficient by dynamic offloading? (Abstract)

Jie Tang , Department of Computer Science and Engineering, University of California, Riverside, USA
Chen Liu , Department of Electrical & Computer Engineering, Clarkson University, Potsdam, USA
Jean-Luc Gaudiot , Department of Electrical, Engineering and Computer Science, University of California, Irvine, USA
pp. 156-157

Automatic frame rate-based DVFS of game (Abstract)

Zhinan Cheng , Department of Computer Science and Technology, USTC, Hefei, 230027, China
Xi Li , Department of Computer Science and Technology, USTC, Hefei, 230027, China
Beilei Sun , Department of Computer Science and Technology, USTC, Hefei, 230027, China
Ce Gao , Department of Computer Science and Technology, USTC, Hefei, 230027, China
Jiachen Song , Department of Computer Science and Technology, USTC, Hefei, 230027, China
pp. 158-159

MultiExplorer: A tool set for multicore system-on-chip design exploration (Abstract)

Rodrigo Devigo , College of Computing - Federal University of Mato Grosso do Sul, Brazil
Liana Duenha , College of Computing - Federal University of Mato Grosso do Sul, Brazil
Rodolfo Azevedo , Institute of Computing - State University of Campinas, Brazil
Ricardo Santos , College of Computing - Federal University of Mato Grosso do Sul, Brazil
pp. 160-161

Noxim: An open, extensible and cycle-accurate network on chip simulator (Abstract)

Vincenzo Catania , University of Catania, Italy
Andrea Mineo , University of Catania, Italy
Salvatore Monteleone , University of Catania, Italy
Maurizio Palesi , Kore University, Enna, Italy
Davide Patti , University of Catania, Italy
pp. 162-163

GPU kernels for high-speed 4-bit astrophysical data processing (Abstract)

Peter Klages , Dunlap Institute for Astronomy and Astrophysics, University of Toronto, ON, Canada
Kevin Bandura , Department of Physics, McGill University, Montréal, QC, Canada
Nolan Denman , Dunlap Institute for Astronomy and Astrophysics, University of Toronto, ON, Canada
Andre Recnik , Dunlap Institute for Astronomy and Astrophysics, University of Toronto, ON, Canada
Jonathan Sievers , Astrophysics and Cosmology Research Unit, University of KwaZulu-Natal, Durban, South Africa
Keith Vanderlinde , Dunlap Institute for Astronomy and Astrophysics, University of Toronto, ON, Canada
pp. 164-165

Loop coarsening in C-based High-Level Synthesis (Abstract)

Moritz Schmid , Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander University Erlangen-Nürnberg (FAU), Germany
Oliver Reiche , Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander University Erlangen-Nürnberg (FAU), Germany
Frank Hannig , Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander University Erlangen-Nürnberg (FAU), Germany
Jurgen Teich , Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander University Erlangen-Nürnberg (FAU), Germany
pp. 166-173

An interpolation-based approach to multi-parameter performance modeling for heterogeneous systems (Abstract)

Dylan Rudolph , Department of Electrical and Computer Engineering, University of Florida, USA
Greg Stitt , Department of Electrical and Computer Engineering, University of Florida, USA
pp. 174-180

Mixed-length SIMD code generation for VLIW architectures with multiple native vector-widths (Abstract)

Erkan Diken , Eindhoven University of Technology, The Netherlands
Martin J. O'Riordan , Movidius Ltd., 1st Floor, O'Connell Bridge House, D'Olier St, Dublin 2, Ireland
Roel Jordans , Eindhoven University of Technology, The Netherlands
Lech Jozwiak , Eindhoven University of Technology, The Netherlands
Henk Corporaal , Eindhoven University of Technology, The Netherlands
David Moloney , Movidius Ltd., 1st Floor, O'Connell Bridge House, D'Olier St, Dublin 2, Ireland
pp. 181-188

Comparative analysis of OpenCL vs. HDL with image-processing kernels on Stratix-V FPGA (Abstract)

Kenneth Hill , NSF Center for High-Performance Reconfigurable Computing, ECE Dept., University of Florida, Gainesville, USA
Stefan Craciun , NSF Center for High-Performance Reconfigurable Computing, ECE Dept., University of Florida, Gainesville, USA
Alan George , NSF Center for High-Performance Reconfigurable Computing, ECE Dept., University of Florida, Gainesville, USA
Herman Lam , NSF Center for High-Performance Reconfigurable Computing, ECE Dept., University of Florida, Gainesville, USA
pp. 189-193

On-demand fault-tolerant loop processing on massively parallel processor arrays (Abstract)

Alexandru Tanase , Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany
Michael Witterauf , Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany
Jurgen Teich , Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany
Frank Hannig , Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany
Vahid Lari , Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany
pp. 194-201

A scheduling and binding heuristic for high-level synthesis of fault-tolerant FPGA applications (Abstract)

Aniruddha Shastri , Department of Electrical and Computer Engineering, University of Florida, Gainesville, USA
Greg Stitt , Department of Electrical and Computer Engineering, University of Florida, Gainesville, USA
Eduardo Riccio , Department of Electrical and Computer Engineering, University of Florida, Gainesville, USA
pp. 202-209

Reconfigurable acceleration of fitness evaluation in trading strategies (Abstract)

Andreea Ingrid Funie , Department of Computing, Imperial College London, 180 Queen's Gate, SW7 2AZ, UK
Paul Grigoras , Department of Computing, Imperial College London, 180 Queen's Gate, SW7 2AZ, UK
Pavel Burovskiy , Department of Computing, Imperial College London, 180 Queen's Gate, SW7 2AZ, UK
Wayne Luk , Department of Computing, Imperial College London, 180 Queen's Gate, SW7 2AZ, UK
Mark Salmon , Department of Computing, Imperial College London, 180 Queen's Gate, SW7 2AZ, UK
pp. 210-217

An efficient architecture solution for low-power real-time background subtraction (Abstract)

Hamed Tabkhi , Department of Electrical and Computer Engineering, Northeastern University, Boston (MA), USA
Majid Sabbagh , Department of Electrical and Computer Engineering, Northeastern University, Boston (MA), USA
Gunar Schirner , Department of Electrical and Computer Engineering, Northeastern University, Boston (MA), USA
pp. 218-225

Large-scale packet classification on FPGA (Abstract)

Shijie Zhou , Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, 90089, USA
Yun R. Qu , Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, 90089, USA
Viktor K. Prasanna , Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, 90089, USA
pp. 226-233

Efficient implementation of structured long block-length LDPC codes (Abstract)

Andrew J. Wong , Department of Electrical and Computer Engineering, McGill University, Montreal, Qc, Canada, H3A 0E9
Saied Hemati , Department of Electrical and Computer Engineering, University of Idaho, Moscow, USA, 83844
Warren J. Gross , Department of Electrical and Computer Engineering, McGill University, Montreal, Qc, Canada, H3A 0E9
pp. 234-238

Energy optimization of parallel k-means clustering algorithm on FPGA (Abstract)

Andrea Sanny , Ming Hsieh Dept. of Electrical Engineering, University of Southern California, USA
Yi-Hua E. Yang , Xilinx Inc., Santa Clara, CA, USA
Viktor K. Prasanna , Ming Hsieh Dept. of Electrical Engineering, University of Southern California, USA
pp. 239-243

Author index (PDF)

pp. 1-2
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