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2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP) (2015)
Toronto, ON, Canada
July 27, 2015 to July 29, 2015
ISSN: 2160-052X
ISBN: 978-1-4799-1924-6
pp: 111-115
Ran Wang , Department of Electrical and Computer Engineering, University of Alberta, Edmonton, T6G 2V4, Canada
Jie Han , Department of Electrical and Computer Engineering, University of Alberta, Edmonton, T6G 2V4, Canada
Bruce Cockburn , Department of Electrical and Computer Engineering, University of Alberta, Edmonton, T6G 2V4, Canada
Duncan Elliott , Department of Electrical and Computer Engineering, University of Alberta, Edmonton, T6G 2V4, Canada
ABSTRACT
Vector quantization (VQ) is a general data compression technique that has a scalable implementation complexity and potentially a high compression ratio. In this paper, a novel implementation of VQ using stochastic circuits is proposed and its performance is evaluated. The stochastic and binary designs are compared for the same compression quality and the circuits are synthesized for an industrial 28-nm cell library. The effects of varying the sequence length of the stochastic design are studied with respect to the performance metric of throughput per area (TPA). When a shortened 512-bit encoding sequence is used to obtain a lower quality compression, the TPA is about 2.60 times that of the binary implementation with the same quality as that of the stochastic implementation measured by the L1 norm error (i.e., the first-order error). Thus, the stochastic implementation outperforms the conventional binary design in terms of TPA for a relatively low compression quality. By exploiting the progressive precision feature of a stochastic circuit, a readily scalable processing quality can be attained by simply halting the computation after different numbers of clock cycles.
INDEX TERMS
Image coding, Indexes, Vector quantization, Calculators, Clocks, Hardware, Encoding
CITATION

R. Wang, J. Han, B. Cockburn and D. Elliott, "Stochastic circuit design and performance evaluation of vector quantization," 2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP), Toronto, ON, Canada, 2015, pp. 111-115.
doi:10.1109/ASAP.2015.7245717
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