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2014 IEEE 25th International Conference on Application-specific Systems, Architectures and Processors (ASAP) (2014)
Zurich, Switzerland
June 18, 2014 to June 20, 2014
ISSN: 2160-052X
ISBN: 978-1-4799-3609-0
TABLE OF CONTENTS

[Front cover] (PDF)

pp. c1

Title page (PDF)

pp. 1

Hub page (PDF)

pp. 1

Session list (PDF)

pp. 1

Table of contents (PDF)

pp. 1-10

Author index (PDF)

pp. 1-5

End breaker (PDF)

pp. 1

About CP (PDF)

pp. 1

Map-reduce processing of k-means algorithm with FPGA-accelerated computer cluster (Abstract)

Yuk-Ming Choi , Department of Electrical and Electronic Engineering, The University of Hong Kong, Hong Kong
Hayden Kwok-Hay So , Department of Electrical and Electronic Engineering, The University of Hong Kong, Hong Kong
pp. 9-16

Adaptive scalable SVD unit for fast processing of large LSE problems (Abstract)

Inaki Bildosola , Grupo de Diseño en Electrónica Digital (GDED), University of the Basque Country (UPV/EHU), Bilbao, Spain
Unai Martinez-Corral , Grupo de Diseño en Electrónica Digital (GDED), University of the Basque Country (UPV/EHU), Bilbao, Spain
Koldo Basterretxea , Dept. Electronics Technology, University of the Basque Country (UPV/EHU), Bilbao, Spain
pp. 17-24

SIR10US: A tightly coupled elliptic-curve cryptography co-processor for the OpenRISC (Abstract)

Michael Gautschi , Integrated Systems Laboratory, ETH Zurich, Gloriastrasse 35, 8092, Switzerland
Michael Muehlberghuber , Integrated Systems Laboratory, ETH Zurich, Gloriastrasse 35, 8092, Switzerland
Andreas Traber , Integrated Systems Laboratory, ETH Zurich, Gloriastrasse 35, 8092, Switzerland
Sven Stucki , Integrated Systems Laboratory, ETH Zurich, Gloriastrasse 35, 8092, Switzerland
Matthias Baer , Integrated Systems Laboratory, ETH Zurich, Gloriastrasse 35, 8092, Switzerland
Renzo Andri , Integrated Systems Laboratory, ETH Zurich, Gloriastrasse 35, 8092, Switzerland
Luca Benini , Integrated Systems Laboratory, ETH Zurich, Gloriastrasse 35, 8092, Switzerland
Beat Muheim , Microelectronics Design Center, ETH Zurich, Gloriastrasse 35, 8092, Switzerland
Hubert Kaeslin , Microelectronics Design Center, ETH Zurich, Gloriastrasse 35, 8092, Switzerland
pp. 25-29

Customizable coarse-grained energy-efficient reconfigurable packet processing architecture (Abstract)

Mohammad Badawi , KTH Royal Institute of Technology, Stockholm, Sweden
Ahmed Hemani , KTH Royal Institute of Technology, Stockholm, Sweden
Zhonghai Lu , KTH Royal Institute of Technology, Stockholm, Sweden
pp. 30-35

Low latency FPGA acceleration of market data feed arbitration (Abstract)

Stewart Denholm , Department of Computing, Imperial College London, UK
Hiroaki Inoue , NEC Corporation, Kawasaki, Japan
Takashi Takenaka , NEC Corporation, Kawasaki, Japan
Tobias Becker , Department of Computing, Imperial College London, UK
Wayne Luk , Department of Computing, Imperial College London, UK
pp. 36-40

Sum-of-product architectures computing just right (Abstract)

Florent de Dinechin , Université de Lyon, INRIA, INSA-Lyon, CITI-INRIA, F-69621, Villeurbanne, France
Matei Istoan , Université de Lyon, INRIA, INSA-Lyon, CITI-INRIA, F-69621, Villeurbanne, France
Abdelbassat Massouri , Université de Lyon, INRIA, INSA-Lyon, CITI-INRIA, F-69621, Villeurbanne, France
pp. 41-47

Pipelined modular multiplier supporting multiple standard prime fields (Abstract)

H. Alrimeih , Cyber Security Centre, KACST, Riyadh 11442, Saudi Arabia
D. Rakhmatov , ECE Department, University of Victoria, British Columbia V8P 5C2, Canada
pp. 48-56

RNS modular multiplication through reduced base extensions (Abstract)

Karim Bigou , INRIA Centre Rennes - Bretagne Atlantique, 6 rue Kerampont, CS 80518, F-22305 Lannion cedex, FRANCE
Arnaud Tisserand , CNRS, University Rennes 1, 6 rue Kerampont, CS 80518, F-22305 Lannion cedex, FRANCE
pp. 57-62

On the computation of the reciprocal of floating point expansions using an adapted Newton-Raphson iteration (Abstract)

Mioara Joldes , CNRS, lab. LAAS, 7 Avenue du Colonel Roche, 31077 Toulouse, France
Jean-Michel Muller , CNRS, lab. LIP, 46 Allée d'Italie, 69364 Lyon, France
Valentina Popescu , Lab. LAAS-CNRS, 7 Avenue du Colonel Roche, 31077 Toulouse, France
pp. 63-67

Polar baseband receiver for low-end WLAN (Abstract)

A. Altamimi , ECE Department, University of Victoria, British Columbia V8P 5C2, Canada
D. Rakhmatov , ECE Department, University of Victoria, British Columbia V8P 5C2, Canada
M. McGuire , ECE Department, University of Victoria, British Columbia V8P 5C2, Canada
pp. 68-69

Design of a 2D graphics front-end rendering processor (Abstract)

Yun-Nan Chang , Department of Computer Science and Engineering, National Sun Yat-sen University, Kaohsiung, 80424, Taiwan
Ting-Chi Tong , Department of Computer Science and Engineering, National Sun Yat-sen University, Kaohsiung, 80424, Taiwan
pp. 70-71

Performance modeling of virtualized custom logic computations (Abstract)

Michael J. Hall , Department of Computer Science & Engineering, Washington University in St. Louis, USA
Roger D. Chamberlain , Department of Computer Science & Engineering, Washington University in St. Louis, USA
pp. 72-73

HICore1: “Safety on a chip” turnkey solution for industrial control (Abstract)

Ali Hayek , University of Kassel, Computer Architecture and System Programming, Germany
Bashier Machmur , University of Kassel, Computer Architecture and System Programming, Germany
Michael Schreiber , University of Kassel, Computer Architecture and System Programming, Germany
Josef Borcsok , University of Kassel, Computer Architecture and System Programming, Germany
Stefan Golz , HIMA Paul Hildebrandt GmbH + Co KG, Chip-based Solutions, Brühl, Germany
Mario Epp , HIMA Paul Hildebrandt GmbH + Co KG, Chip-based Solutions, Brühl, Germany
pp. 74-75

A reconfigurable network-on-chip architecture for heterogeneous CMPs in the dark-silicon era (Abstract)

Mehdi Modarressi , Department of Electrical and Computer Engineering, College of Engineering, University of Tehran, Iran
Hamid Sarbazi-Azad , Department of Computer Engineering, Sharif University of Technology, Tehran, Iran
pp. 76-77

Randomized windows for secure scalar multiplication on elliptic curves (Abstract)

Simon Pontie , Univ. Grenoble Alpes, TIMA, F-38031, CNRS, TIMA, F-38031, France
Paolo Maistri , Univ. Grenoble Alpes, TIMA, F-38031, CNRS, TIMA, F-38031, France
pp. 78-79

Virtual semi-concurrent self-checking for heterogeneous MPSoC architectures (Abstract)

Mariagiovanna Sami , Politecnico di Milano - Dipartimento di Elettronica, Informazione e Bioingegneria, Italy
Gianluca Palermo , Politecnico di Milano - Dipartimento di Elettronica, Informazione e Bioingegneria, Italy
pp. 80-81

Distributed synchronization for message-passing based embedded multiprocessors (Abstract)

Hao Xiao , College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics, China 210016
Tsuyoshi Isshiki , Tokyo Institute of Technology, Japan 152-8552
Dongju Li , Tokyo Institute of Technology, Japan 152-8552
Hiroaki Kunieda , Tokyo Institute of Technology, Japan 152-8552
Guanyu Zhu , Shannon Lab, Huawei, China
pp. 82-83

Performance modeling for highly-threaded many-core GPUs (Abstract)

Lin Ma , Department of Computer Science and Engineering, Washington University in St. Louis, USA
Roger D. Chamberlain , Department of Computer Science and Engineering, Washington University in St. Louis, USA
Kunal Agrawal , Department of Computer Science and Engineering, Washington University in St. Louis, USA
pp. 84-91

Analyzing the energy-efficiency of dense linear algebra kernels by power-profiling a hybrid CPU/FPGA system (Abstract)

Heiner Giefers , IBM Research - Zurich, Switzerland
Raphael Polig , IBM Research - Zurich, Switzerland
Christoph Hagleitner , IBM Research - Zurich, Switzerland
pp. 92-99

Coordinated and adaptive power gating and dynamic voltage scaling for energy minimization (Abstract)

Nathaniel A. Conos , Computer Science Department, University of California, Los Angeles, USA
Saro Meguerdichian , Computer Science Department, University of California, Los Angeles, USA
Miodrag Potkonjak , Computer Science Department, University of California, Los Angeles, USA
pp. 100-107

A case against small data types in GPGPUs (Abstract)

Ahmad Lashgar , Department of Electrical and Computer Engineering, University of Victoria, Canada
Amirali Baniasadi , Department of Electrical and Computer Engineering, University of Victoria, Canada
pp. 108-113

He-P2012: Architectural heterogeneity exploration on a scalable many-core platform (Abstract)

Francesco Conti , Department of Electrical, Electronic and Information Engineering, University of Bologna, Italy
Chuck Pilkington , STMicroelectronics, Ottawa, Canada
Andrea Marongiu , Department of Electrical, Electronic and Information Engineering, University of Bologna, Italy
Luca Benini , Department of Electrical, Electronic and Information Engineering, University of Bologna, Italy
pp. 114-120

Function-Level Processor (FLP): Raising efficiency by operating at function granularity for market-oriented MPSoC (Abstract)

Hamed Tabkhi , Department of Electrical and Computer Engineering, Northeastern University, Boston (MA), USA
Robert Bushey , Embedded Systems Products and Technology, Analog Devices Inc. (ADI), Norwood (MA), USA
Gunar Schirner , Department of Electrical and Computer Engineering, Northeastern University, Boston (MA), USA
pp. 121-130

Design of an accelerator-rich architecture by integrating multiple heterogeneous coarse grain reconfigurable arrays over a network-on-chip (Abstract)

Waqar Hussain , Department of Electronics and Communications Engineering, Tampere University of Technology, FI-33101, Finland
Roberto Airoldi , Department of Electronics and Communications Engineering, Tampere University of Technology, FI-33101, Finland
Henry Hoffmann , Department of Computer Science, University of Chicago, IL-60637, USA
Tapani Ahonen , Department of Electronics and Communications Engineering, Tampere University of Technology, FI-33101, Finland
Jari Nurmi , Department of Electronics and Communications Engineering, Tampere University of Technology, FI-33101, Finland
pp. 131-138

Fault-tolerant on-chip networking through adaptive routing and dynamic partial reconfiguration (Abstract)

Taimour Wehbe , Department of Electrical and Computer Engineering, Villanova University, 800 E Lancaster Avenue, PA 19085, USA
Xiaofang Wang , Department of Electrical and Computer Engineering, Villanova University, 800 E Lancaster Avenue, PA 19085, USA
pp. 139-146

Secure interrupts on low-end microcontrollers (Abstract)

Ruan de Clercq , KU Leuven, Department of Electrical Engineering (ESAT), COSIC, Belgium
Frank Piessens , KU Leuven, Department of Computer Science, DistriNet, Belgium
Dries Schellekens , KU Leuven, Department of Electrical Engineering (ESAT), COSIC, Belgium
Ingrid Verbauwhede , KU Leuven, Department of Electrical Engineering (ESAT), COSIC, Belgium
pp. 147-152

On the characterization of OpenCL dwarfs on fixed and reconfigurable platforms (Abstract)

Konstantinos Krommydas , Department of Computer Science, Virginia Tech, USA
Wu-chun Feng , Department of Computer Science, Virginia Tech, USA
Muhsen Owaida , Department of Electrical and Computer Engineering, University of Thessaly, Greece
Christos D. Antonopoulos , Department of Electrical and Computer Engineering, University of Thessaly, Greece
Nikolaos Bellas , Department of Electrical and Computer Engineering, University of Thessaly, Greece
pp. 153-160

Evaluating orthogonality between application auto-tuning and run-time resource management for adaptive OpenCL applications (Abstract)

Edoardo Paone , Politecnico di Milano - Dipartimento di Elettronica, Informazione e Bioingegneria, Italy
Davide Gadioli , Politecnico di Milano - Dipartimento di Elettronica, Informazione e Bioingegneria, Italy
Gianluca Palermo , Politecnico di Milano - Dipartimento di Elettronica, Informazione e Bioingegneria, Italy
Vittorio Zaccaria , Politecnico di Milano - Dipartimento di Elettronica, Informazione e Bioingegneria, Italy
Cristina Silvano , Politecnico di Milano - Dipartimento di Elettronica, Informazione e Bioingegneria, Italy
pp. 161-168

Efficient application mapping on CGRAs based on backward simultaneous scheduling/binding and dynamic graph transformations (Abstract)

Thomas Peyret , CEA, LIST, Laboratoire Capteurs et Architectures Électronique, F-91191 Gif-sur-Yvette, France
Gwenole Corre , CEA, LIST, Laboratoire Capteurs et Architectures Électronique, F-91191 Gif-sur-Yvette, France
Mathieu Thevenin , CEA, LIST, Laboratoire Capteurs et Architectures Électronique, F-91191 Gif-sur-Yvette, France
Kevin Martin , Université de Bretagne-Sud, Lab-STICC, Lorient, France
Philippe Coussy , Université de Bretagne-Sud, Lab-STICC, Lorient, France
pp. 169-172

Domain-specific augmentations for High-Level Synthesis (Abstract)

Moritz Schmid , University of Erlangen-Nürnberg, 91058, Germany
Alexandru Tanase , University of Erlangen-Nürnberg, 91058, Germany
Frank Hannig , University of Erlangen-Nürnberg, 91058, Germany
Jurgen Teich , University of Erlangen-Nürnberg, 91058, Germany
Vivek Singh Bhadouria , Department of Electronics and Communication Engineering, National Institute of Technology, Agartala, India, 799055
Dibyendu Ghoshal , Department of Electronics and Communication Engineering, National Institute of Technology, Agartala, India, 799055
pp. 173-177

Virtual science on the move: Interactive access to simulations on supercomputers (Abstract)

Junyi Han , School of Computer Science, Killburn Building, the University of Manchester, Oxford Road, M13 9PL, UK
Robert Haines , School of Computer Science, Killburn Building, the University of Manchester, Oxford Road, M13 9PL, UK
Adel Salhli , School of Computer Science, Killburn Building, the University of Manchester, Oxford Road, M13 9PL, UK
John Martin Brooke , School of Computer Science, Killburn Building, the University of Manchester, Oxford Road, M13 9PL, UK
Bruce D'Amora , IBM, T. J. Watson Research Centre, Yorktown Heights, N.Y. 10598, USA
Bob Danani , IBM, Melbourne Research Lab, Australia
pp. 178-179

A practical network intrusion detection system for inline FPGAs on 10GbE network adapters (Abstract)

Keerthan Jaic , Holcombe Department of of Electrical and Computer Engineering, Clemson University, South Carolina, 29634, USA
Melissa C. Smith , Holcombe Department of of Electrical and Computer Engineering, Clemson University, South Carolina, 29634, USA
Nilim Sarma , Holcombe Department of of Electrical and Computer Engineering, Clemson University, South Carolina, 29634, USA
pp. 180-181

An approach of processor core customization for stencil computation (Abstract)

Yanhua Li , Department of Computer Science and Technology, Tsinghua University, Beijing, China
Youhui Zhang , Department of Computer Science and Technology, Tsinghua University, Beijing, China
Jianfeng Yang , Department of Computer Science and Technology, Tsinghua University, Beijing, China
Wayne Luk , Department of Computing,Imperial College, London, UK
Guangwen Yang , Department of Computer Science and Technology, Tsinghua University, Beijing, China
Weimin Zheng , Department of Computer Science and Technology, Tsinghua University, Beijing, China
pp. 182-183

SWAPHI: Smith-waterman protein database search on Xeon Phi coprocessors (Abstract)

Yongchao Liu , Institut für Informatik, Johannes Gutenberg Universität Mainz, Germany
Bertil Schmidt , Institut für Informatik, Johannes Gutenberg Universität Mainz, Germany
pp. 184-185

A scalable and compact systolic architecture for linear solvers (Abstract)

Kevin S. H. Ong , School of Computer Engineering, Nanyang Technological University, Singapore
Suhaib A. Fahmy , School of Computer Engineering, Nanyang Technological University, Singapore
Keck-Voon Ling , School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore
pp. 186-187

Efficient and scalable CGRA-based implementation of Column-wise Givens Rotation (Abstract)

Zoltan Endre Rakossy , Institute for Communication Technologies and Embedded Systems (ICE), RWTH University Aachen, Germany
Farhad Merchant , CADLab, Indian Institute of Science, Bangalore 560012, India
Axel Acosta-Aponte , Institute for Communication Technologies and Embedded Systems (ICE), RWTH University Aachen, Germany
S.K. Nandy , CADLab, Indian Institute of Science, Bangalore 560012, India
Anupam Chattopadhyay , Institute for Communication Technologies and Embedded Systems (ICE), RWTH University Aachen, Germany
pp. 188-189

Bandwidth compression of multiple numerical data streams for high performance custom computing (Abstract)

Tomohiro Ueno , Graduate School of Information Sciences, Tohoku University, Sendai, Japan
Ryo Ito , Graduate School of Information Sciences, Tohoku University, Sendai, Japan
Kentaro Sano , Graduate School of Information Sciences, Tohoku University, Sendai, Japan
Satoru Yamamoto , Graduate School of Information Sciences, Tohoku University, Sendai, Japan
pp. 190-191

A customized GPU acceleration of the princeton ocean model (Abstract)

Shizhen Xu , Ministry of Education Key Laboratory for Earth System Modeling, China
Xiaomeng Huang , Ministry of Education Key Laboratory for Earth System Modeling, China
Yan Zhang , Ministry of Education Key Laboratory for Earth System Modeling, China
Yong Hu , Ministry of Education Key Laboratory for Earth System Modeling, China
Guangwen Yang , Ministry of Education Key Laboratory for Earth System Modeling, China
pp. 192-193

Pipelined reconfigurable accelerator for ordinal pattern encoding (Abstract)

Ce Guo , Department of Computing, Imperial College London, United Kingdom
Wayne Luk , Department of Computing, Imperial College London, United Kingdom
Stephen Weston , Maxeler Technologies, London, United Kingdom
pp. 194-201

Energy efficient canonical huffman encoding (Abstract)

Janarbek Matai , Department of Computer Science and Engineering, University of California, San Diego, USA
Joo-Young Kim , Microsoft Research, USA
Ryan Kastner , Department of Computer Science and Engineering, University of California, San Diego, USA
pp. 202-209

Flexible multistandard FEC processor design with ASIP methodology (Abstract)

Zhenzhi Wu , Department of Electrical Engineering, Linköping University, SE-58 183, Sweden
Dake Liu , Department of Electrical Engineering, Linköping University, SE-58 183, Sweden
pp. 210-218

Energy-efficient gear-shift LDPC decoders (Abstract)

Kevin Cushon , Institutionen för Systemteknik, Linköping University, Sweden
Saied Hemati , Dept. of Electrical & Computer Engineering, University of Idaho, Moscow, USA
Shie Mannor , Dept. of Electrical Engineering, Technion, Haifa, Israel
Warren J. Gross , Dept. of Electrical & Computer Engineering, McGill University, Montreal, Canada
pp. 219-223

Exploring DMA-assisted prefetching strategies for software caches on multicore clusters (Abstract)

Christian Pinto , DEI Deparment, University of Bologna, Italy
Luca Benini , DEI Deparment, University of Bologna, Italy
pp. 224-231

A compression-based morphable PCM architecture for improving resistance drift tolerance (Abstract)

Majid Jalili , HPCAN Lab, Department of Computer Engineering, Sharif University of Technology, Tehran, Iran
Hamid Sarbazi-Azad , HPCAN Lab, Department of Computer Engineering, Sharif University of Technology, Tehran, Iran
pp. 232-239

PVMC: Programmable Vector Memory Controller (Abstract)

Tassadaq Hussain , Computer Sciences, Barcelona Supercomputing Center, Spain
Oscar Palomar , Computer Sciences, Barcelona Supercomputing Center, Spain
Osman Unsal , Computer Sciences, Barcelona Supercomputing Center, Spain
Adrian Cristal , Computer Sciences, Barcelona Supercomputing Center, Spain
Eduard Ayguade , Computer Sciences, Barcelona Supercomputing Center, Spain
Mateo Valero , Computer Sciences, Barcelona Supercomputing Center, Spain
pp. 240-247

Understanding the design space of DRAM-optimized hardware FFT accelerators (Abstract)

Berkin Akin , ECE Department, Carnegie Mellon University, Pittsburgh, PA, USA
Franz Franchetti , ECE Department, Carnegie Mellon University, Pittsburgh, PA, USA
James C. Hoe , ECE Department, Carnegie Mellon University, Pittsburgh, PA, USA
pp. 248-255

Quality-aware video decoding on thermally-constrained MPSoC platforms (Abstract)

Deepak Gangadharan , Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander University, Germany
Jurgen Teich , Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander University, Germany
Samarjit Chakraborty , Institute for Real-Time Computer Systems, TU Munich, Germany
pp. 256-263

Combining flexibility with low power: Dataflow and wide-pipeline LDPC decoding engines in the Gbit/s era (Abstract)

Joao Andrade , Instituto de Telecomunicações, DEEC, University of Coimbra, Portugal
Frederico Pratas , INESC-ID, Instituto Superior Técnico, Universidade de Lisboa, Portugal
Gabriel Falcao , Instituto de Telecomunicações, DEEC, University of Coimbra, Portugal
Vitor Silva , Instituto de Telecomunicações, DEEC, University of Coimbra, Portugal
Leonel Sousa , INESC-ID, Instituto Superior Técnico, Universidade de Lisboa, Portugal
pp. 264-269
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