The Community for Technology Leaders
2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors (2013)
Washington, DC, USA USA
June 5, 2013 to June 7, 2013
ISSN: 2160-0511
ISBN: 978-1-4799-0494-5
TABLE OF CONTENTS
Papers

Table of contents (Abstract)

pp. 1-11

Detailed author index (Abstract)

pp. 1-36

Loop program mapping and compact code generation for programmable hardware accelerators (Abstract)

Srinivas Boppu , Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, Germany
Frank Hannig , Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, Germany
Jurgen Teich , Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, Germany
pp. 10-17

Cache partitioning and scheduling for energy optimization of real-time MPSoCs (Abstract)

Gang Chen , TU Munich, Germany
Kai Huang , TU Munich, Germany
Jia Huang , Fortiss GmbH, Germany
Alois Knoll , TU Munich, Germany
pp. 35-41

Design space exploration for reliable mm-wave wireless NoC architectures (Abstract)

Paul Wettin , School of Electrical Engineering and Computer Science, Washington State University, Pullman, USA
Partha Pratim Pande , School of Electrical Engineering and Computer Science, Washington State University, Pullman, USA
Deukhyoun Heo , School of Electrical Engineering and Computer Science, Washington State University, Pullman, USA
Benjamin Belzer , School of Electrical Engineering and Computer Science, Washington State University, Pullman, USA
Sujay Deb , Department of Electronics and Communications Engineering, Indraprastha Institute of Information Technology, Delhi, India
Amlan Ganguly , Department of Computer Engineering, Rochester Institute of Technology, Rochester, USA
pp. 79-82

Virtual finite-state-machine architectures for fast compilation and portability (Abstract)

Lu Hao , Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA
Greg Stitt , Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA
pp. 91-94

Selective validations for efficient protections on Coarse-Grained Reconfigurable Architectures (Abstract)

Jihoon Kang , Department of Computer Science, Yonsei University, Seoul, Republic of Korea
Yohan Ko , Department of Computer Science, Yonsei University, Seoul, Republic of Korea
Jongwon Lee , School of Electrical Engineering, Seoul National University, Seoul, Republic of Korea
Yongjoo Kim , Electronics and Telecommunications Research Institute, Republic of Korea
Hwisoo So , Department of Computer Science, Yonsei University, Seoul, Republic of Korea
Kyoungwoo Lee , Department of Computer Science, Yonsei University, Seoul, Republic of Korea
Yunheung Paek , School of Electrical Engineering, Seoul National University, Seoul, Republic of Korea
pp. 95-98

OCP: Offload Co-Processor for energy efficiency in embedded mobile systems (Abstract)

Jie Tang , Intel, Beijing, China
Chen Liu , Clarkson University Potsdam, NY, USA
Yu-Liang Chou , University of California, Irvine, CA, USA
Shaoshan Liu , Microsoft, Redmond, WA, USA
pp. 107-110

Synthesizing accurate floating-point formulas (Abstract)

Arnault Ioualalen , Univ. Perpignan Via Domitia, Digits, Architectures et Logiciels Informatiques, F-66860, Perpignan, France
Matthieu Martel , Univ. Perpignan Via Domitia, Digits, Architectures et Logiciels Informatiques, F-66860, Perpignan, France
pp. 113-116

A compact and scalable RNS architecture (Abstract)

Pedro Miguens Matutino , ISEL / INESC-ID / IST, Technical University of Lisbon, Lisbon, Portugal
Ricardo Chaves , INESC-ID / IST, Technical University of Lisbon, Lisbon, Portugal
Leonel Sousa , INESC-ID / IST, Technical University of Lisbon, Lisbon, Portugal
pp. 125-132
Papers

Hardware acceleration for Just-In-Time compilation on heterogeneous embedded systems (Abstract)

Alexandre Carbon , CEA, LIST, Embedded Computing Laboratory, F-91191 Gif-sur-Yvette, France
Yves Lhuillier , CEA, LIST, Embedded Computing Laboratory, F-91191 Gif-sur-Yvette, France
Henri-Pierre Charles , CEA, LIST, Embedded Software Laboratory, F-91191 Gif-sur-Yvette, France
pp. 203-210

Microkernel hypervisor for a hybrid ARM-FPGA platform (Abstract)

Khoa Dang Pham , School of Computer Engineering, Nanyang Technological University, Singapore
Abhishek Kumar Jain , School of Computer Engineering, Nanyang Technological University, Singapore
Jin Cui , TUM CREATE Centre for Electromobility, Singapore
Suhaib A. Fahmy , School of Computer Engineering, Nanyang Technological University, Singapore
Douglas L. Maskell , School of Computer Engineering, Nanyang Technological University, Singapore
pp. 219-226

Novel Multi-Layer Network Decomposition boosting acceleration of multi-core algorithms (Abstract)

Athanasios K. Grivas , School of Electrical and Electronic Engineering, Newcastle University, UK
Terrence Mak , Department of Computer Science and Engineering, The Chinese University of Hong Kong, China
Alex Yakovlev , School of Electrical and Electronic Engineering, Newcastle University, UK
Jonny Wray , e-Therapeutics plc, UK
pp. 249-252

On the performance of code block segmentation for LTE-advanced (Abstract)

Karlo G. Lenzi , DRC - Convergent Networks Department, CPqD - Research and Development Center on Telecommunication, Campinas, SP - Brazil
Felipe A. P. Figueiredo , DRC - Convergent Networks Department, CPqD - Research and Development Center on Telecommunication, Campinas, SP - Brazil
Jose A. B. Filho , DRC - Convergent Networks Department, CPqD - Research and Development Center on Telecommunication, Campinas, SP - Brazil
Fabricio L. Figueiredo , DRC - Convergent Networks Department, CPqD - Research and Development Center on Telecommunication, Campinas, SP - Brazil
pp. 253-256

Linear algebra computations in heterogeneous systems (Abstract)

Sam Skalicky , Department of Computer Engineering, Rochester Institute of Technology, Rochester, NY, USA
Sonia Lopez , Department of Computer Engineering, Rochester Institute of Technology, Rochester, NY, USA
Marcin Lukowiak , Department of Computer Engineering, Rochester Institute of Technology, Rochester, NY, USA
James Letendre , Department of Computer Engineering, Rochester Institute of Technology, Rochester, NY, USA
David Gasser , Department of Computer Engineering, Rochester Institute of Technology, Rochester, NY, USA
pp. 273-276

[USB welcome] (Abstract)

pp. 1

Hub page (Abstract)

pp. 1

Session list (Abstract)

pp. 1

Conference committee (Abstract)

pp. 1-3

Highly scalable on-the-fly interleaved address generation for UMTS/HSPA+ parallel turbo decoder (Abstract)

Aida Vosoughi , Department of Electrical and Computer Engineering, Rice University, Houston, Texas, USA
Guohui Wang , Department of Electrical and Computer Engineering, Rice University, Houston, Texas, USA
Hao Shen , Department of Electrical and Computer Engineering, Rice University, Houston, Texas, USA
Joseph R. Cavallaro , Department of Electrical and Computer Engineering, Rice University, Houston, Texas, USA
Yuanbin Guo , Wireless R&D, US Research Center, Futurewei Technologies, Plano, Texas, USA
pp. 356-362

Modelling communication overhead for accessing local memories in hardware accelerators (Abstract)

Alok Prakash , Center for High Performance Embedded Systems, School of Computer Engineering, NTU, Singapore
Siew-Kei Lam , Center for High Performance Embedded Systems, School of Computer Engineering, NTU, Singapore
Thambipillai Srikanthan , Center for High Performance Embedded Systems, School of Computer Engineering, NTU, Singapore
Christopher T. Clarke , Department of EES, University of Bath, United Kingdom
pp. 31-34

Migration-aware loop retiming for STT-RAM based hybrid cache for embedded systems (Abstract)

Keni Qiu , Department of Computer Science, City University of Hong Kong, Hong Kong, China
Mengying Zhao , Department of Computer Science, City University of Hong Kong, Hong Kong, China
Chenchen Fu , Department of Computer Science, City University of Hong Kong, Hong Kong, China
Liang Shi , Department of Computer Science, City University of Hong Kong, Hong Kong, China
Chun Jason Xue , Department of Computer Science, City University of Hong Kong, Hong Kong, China
pp. 83-86

Reduce, Reuse, Recycle (R3): A design methodology for Sparse Matrix Vector Multiplication on reconfigurable platforms (Abstract)

Kevin Townsend , Department of Electrical and Computer Engineering, Iowa State University, Ames, IA, USA
Joseph Zambreno , Department of Electrical and Computer Engineering, Iowa State University, Ames, IA, USA
pp. 185-191

An efficient & reconfigurable FPGA and ASIC implementation of a spectral Doppler ultrasound imaging system (Abstract)

Adam Page , Dept. of Computer Science & Electrical Engineering, University of Maryland, Baltimore County, Baltimore City, USA
Tinoosh Mohsenin , Dept. of Computer Science & Electrical Engineering, University of Maryland, Baltimore County, Baltimore City, USA
pp. 198-202

A comparison of correntropy-based feature tracking on FPGAs and GPUs (Abstract)

Patrick Cooke , Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL USA
Jeremy Fowers , Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL USA
Greg Stitt , Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL USA
Lee Hunt , Prioria, Inc., Gainesville, FL USA
pp. 237-240

Accelerating nonlinear diffusion tensor estimation for medical image processing using high performance GPU clusters (Abstract)

Vinh Q. Dang , Department of Electrical Engineering and Computer Science, The Catholic University of America, Washington, DC 20064, USA
Esam El-Araby , Department of Electrical Engineering and Computer Science, The Catholic University of America, Washington, DC 20064, USA
Lam H. Dao , Department of Electrical Engineering and Computer Science, The Catholic University of America, Washington, DC 20064, USA
Lin-Ching Chang , Department of Electrical Engineering and Computer Science, The Catholic University of America, Washington, DC 20064, USA
pp. 265-268

FPGA and ASIC square root designs for high performance and power efficiency (Abstract)

Shashank Suresh , Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, NJ 07102
Spiridon F. Beldianu , Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, NJ 07102
Sotirios G. Ziavras , Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, NJ 07102
pp. 269-272

A highly efficient, thread-safe software cache implementation for tightly-coupled multicore clusters (Abstract)

Christian Pinto , DEI Department - University of Bologna, Bologna, Viale Risogimento 2, Italy
Luca Benini , DEI Department - University of Bologna, Bologna, Viale Risogimento 2, Italy
pp. 281-288

Exploring hardware support for scaling irregular applications on multi-node multi-core architectures (Abstract)

Simone Secchi , Universita' degli Studi di Cagliari - DIEE, 09123, Cagliari, Italy
Marco Ceriani , Politecnico di Milano - DEI, 20133, Milano, Italy
Antonino Tumeo , Pacific Northwest National Laboratory, Richland, WA
Oreste Villa , Pacific Northwest National Laboratory, Richland, WA
Gianluca Palermo , Politecnico di Milano - DEI, 20133, Milano, Italy
Luigi Raffo , Universita' degli Studi di Cagliari - DIEE, 09123, Cagliari, Italy
pp. 309-313

Design-for-adaptivity of microarchitectures (Abstract)

Maxim Rykunov , School of Electrical and Electronic Engineering Newcastle University, UK
Andrey Mokhov , School of Electrical and Electronic Engineering Newcastle University, UK
Danil Sokolov , School of Electrical and Electronic Engineering Newcastle University, UK
Alex Yakovlev , School of Electrical and Electronic Engineering Newcastle University, UK
Albert Koelmans , School of Electrical and Electronic Engineering Newcastle University, UK
pp. 314-320

GPU acceleration of Data Assembly in Finite Element Methods and its energy implications (Abstract)

Li Tang , Department of Computer Science and Engineering, University of Notre Dame, Notre Dame, Indiana 46556, USA
X. Sharon Hu , Department of Computer Science and Engineering, University of Notre Dame, Notre Dame, Indiana 46556, USA
Danny Z. Chen , Department of Computer Science and Engineering, University of Notre Dame, Notre Dame, Indiana 46556, USA
Michael Niemier , Department of Computer Science and Engineering, University of Notre Dame, Notre Dame, Indiana 46556, USA
Richard F. Barrett , Center for Computing Research, Sandia National Laboratories, Albuquerque, New Mexico 87123, USA
Simon D. Hammond , Center for Computing Research, Sandia National Laboratories, Albuquerque, New Mexico 87123, USA
Genie Hsieh , Center for Computing Research, Sandia National Laboratories, Albuquerque, New Mexico 87123, USA
pp. 321-328

[USB label] (Abstract)

pp. 1

Author index (Abstract)

pp. 1-6

A Reconfigurable Application-specific Instruction-set Processor for Fast Fourier Transform processing (Abstract)

Waqar Hussain , Department of Electronics and Communications Engineering, Tampere University of Technology, FI-33101, Tampere, Finland
Jari Nurmi , Department of Electronics and Communications Engineering, Tampere University of Technology, FI-33101, Tampere, Finland
pp. 339-345

Correctly rounded architectures for Floating-Point multi-operand addition and dot-product computation (Abstract)

Yao Tao , Department of Computer Science and Engineering, Northwestern Polytechnical University, Xi'an, P.R. China
Gao Deyuan , Department of Computer Science and Engineering, Northwestern Polytechnical University, Xi'an, P.R. China
Fan Xiaoya , Department of Computer Science and Engineering, Northwestern Polytechnical University, Xi'an, P.R. China
Jari Nurmi , Department of Electronics and Communications Engineering, Tampere University of Technology, Tampere, Finland
pp. 346-355

Aspect driven compilation for dataflow designs (Abstract)

Paul Grigoras , Department of Computing, Imperial College London, 180 Queen's Gate, London SW7 2AZ, UK
Xinyu Niu , Department of Computing, Imperial College London, 180 Queen's Gate, London SW7 2AZ, UK
Jose G. F. Coutinho , Department of Computing, Imperial College London, 180 Queen's Gate, London SW7 2AZ, UK
Wayne Luk , Department of Computing, Imperial College London, 180 Queen's Gate, London SW7 2AZ, UK
Jacob Bower , Maxeler Technologies Ltd, 1 Down Place, London W6 9JH, UK
Oliver Pell , Maxeler Technologies Ltd, 1 Down Place, London W6 9JH, UK
pp. 18-25

Toward a fast stochastic simulation processor for biochemical reaction networks (Abstract)

Hyungman Park , Electrical and Computer Engineering, The University of Texas at Austin
Andreas Gerstlauer , Electrical and Computer Engineering, The University of Texas at Austin
pp. 50-58

Efficient implementation of cryptographic primitives on the GA144 multi-core architecture (Abstract)

Tobias Schneider , Horst Görtz Institute for IT-Security, Ruhr University Bochum, Germany
Ingo von Maurich , Horst Görtz Institute for IT-Security, Ruhr University Bochum, Germany
Tim Guneysu , Horst Görtz Institute for IT-Security, Ruhr University Bochum, Germany
pp. 67-74

The Denormal Logarithmic Number System (Abstract)

Mark G. Arnold , XLNS Research, PO Box 605 Laramie WY 82070 USA
Sylvain Collange , INRIA, Centre de recherche Rennes - Bretagne Atlantique, Rennes, France
pp. 117-124

An effective New CRT based reverse converter for a novel moduli set {22n+1 − 1, 22n+1, 22n − 1} (Abstract)

Edem Kwedzo Bankas , Department of Computer Science, Faculty of Mathematical Sciences, University for Development Studies, Navrongo, Ghana
Kazeem Alagbe Gbolagade , Department of Computer Science, Faculty of Mathematical Sciences, University for Development Studies, Navrongo, Ghana
Sorin Dan Cotofana , Computer Engineering Lab., Delft University of Technology, Delft, The Netherlands
pp. 142-146

FARHAD: A Fault-Tolerant Power-Aware Hybrid Adder for add intensive applications (Abstract)

Mohammad Hossein Hajkazemi , Department of Electrical and Computer Engineering, University of Victoria, Victoria, Canada
Amirali Baniasadi , Department of Electrical and Computer Engineering, University of Victoria, Victoria, Canada
Hossein Asadi , Department of Computer Engineering, Sharif University of Technology, Tehran, Iran
pp. 153-159

Power optimization of sum-of-products design for signal processing applications (Abstract)

Seok Won Heo , Computer Science Department, University of California at Los Angeles, CA, USA 90095
Suk Joong Huh , Samsung Electronics, Suwon, Korea
Milos D. Ercegovac , Computer Science Department, University of California at Los Angeles, CA, USA 90095
pp. 192-197

Private configuration environments (PCE) for efficient reconfiguration, in CGRAs (Abstract)

Muhammad Adeel Tajammul , Royal Institute of Technology, Sweden
Syed. M. A. H. Jafri , Royal Institute of Technology, Sweden
Ahmed Hemani , Royal Institute of Technology, Sweden
Juha Plosila , University of Turku, Finland
Hannu Tenhunen , Royal Institute of Technology, Sweden
pp. 227-236

BioBlaze: Multi-core SIMD ASIP for DNA sequence alignment (Abstract)

Nuno Neves , IST / INESC-ID, Rua Alves Redol, 9, 1000-029 Lisboa - Portugal
Nuno Sebastiao , IST / INESC-ID, Rua Alves Redol, 9, 1000-029 Lisboa - Portugal
Andre Patricio , IST / INESC-ID, Rua Alves Redol, 9, 1000-029 Lisboa - Portugal
David Matos , IST / INESC-ID, Rua Alves Redol, 9, 1000-029 Lisboa - Portugal
Pedro Tomas , IST / INESC-ID, Rua Alves Redol, 9, 1000-029 Lisboa - Portugal
Paulo Flores , IST / INESC-ID, Rua Alves Redol, 9, 1000-029 Lisboa - Portugal
Nuno Roma , IST / INESC-ID, Rua Alves Redol, 9, 1000-029 Lisboa - Portugal
pp. 241-244

Unifying CORDIC and Box-Muller algorithms: An accurate and efficient Gaussian Random Number generator (Abstract)

Jamshaid Sarwar Malik , ICT, Royal Institute of Technology, Sweden
Ahmed Hemani , ICT, Royal Institute of Technology, Sweden
N. D. Gohar , National University of Sciences and Technology, SEECS, Pakistan
pp. 277-280

A low-power Content-Addressable Memory based on clustered-sparse networks (Abstract)

Hooman Jarollahi , Department of Electrical and Computer Engineering, McGill University, Montreal, Quebec H3A 0E9
Vincent Gripon , Electronics Department, Télécom Bretagne, Brest, France
Naoya Onizawa , Department of Electrical and Computer Engineering, McGill University, Montreal, Quebec H3A 0E9
Warren J. Gross , Department of Electrical and Computer Engineering, McGill University, Montreal, Quebec H3A 0E9
pp. 305-308

The end of indexes (Abstract)

pp. 1

About page (Abstract)

pp. 1

Symbolic parallelization of loop programs for massively parallel processor arrays (Abstract)

Jurgen Teich , Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, Germany
Alexandru Tanase , Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, Germany
Frank Hannig , Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, Germany
pp. 1-9

Enabling development of OpenCL applications on FPGA platforms (Abstract)

Kavya Shagrithaya , Bradley Dept. of ECE, Virginia Tech Blacksburg, VA, USA
Krzysztof Kepa , Bradley Dept. of ECE, Virginia Tech Blacksburg, VA, USA
Peter Athanas , Bradley Dept. of ECE, Virginia Tech Blacksburg, VA, USA
pp. 26-30

Accelerating HAC estimation for multivariate time series (Abstract)

Ce Guo , Department of Computing, Imperial College London, United Kingdom
Wayne Luk , Department of Computing, Imperial College London, United Kingdom
pp. 42-49

A high-speed and large-scale dictionary matching engine for Information Extraction systems (Abstract)

Kanak Agarwal , Austin Research Lab, IBM Corp., Austin, TX, USA
Raphael Polig , Zurich Research Lab, IBM Corp. Zurich, Switzerland
pp. 59-66

iVAMS: Intelligent metamodel-integrated Verilog-AMS for circuit-accurate system-level mixed-signal design exploration (Abstract)

Geng Zheng , NanoSystem Design Laboratory, University of North Texas, Denton, TX 76203, USA
Saraju P. Mohanty , NanoSystem Design Laboratory, University of North Texas, Denton, TX 76203, USA
Elias Kougianos , NanoSystem Design Laboratory, University of North Texas, Denton, TX 76203, USA
Oghenekarho Okobiah , NanoSystem Design Laboratory, University of North Texas, Denton, TX 76203, USA
pp. 75-78

Pseudo-constant logic optimization (Abstract)

Aaron Landy , Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA
Greg Stitt , Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA
pp. 99-102

Fast lossless image compression with Radiation Hardening by hardware/software co-design on platform FPGAs (Abstract)

Andrew G. Schmidt , Information Sciences Institute, University of Southern California
Matthew French , Information Sciences Institute, University of Southern California
pp. 103-106

3D stacked wide-operand adders: A case study (Abstract)

George R. Voicu , Faculty of EE, Mathematics and CS Delft University of Technology Delft, The Netherlands
Mihai Lefter , Faculty of EE, Mathematics and CS Delft University of Technology Delft, The Netherlands
Marius Enachescu , Faculty of EE, Mathematics and CS Delft University of Technology Delft, The Netherlands
Sorin D. Cotofana , Faculty of EE, Mathematics and CS Delft University of Technology Delft, The Netherlands
pp. 133-141

A practical measure of FPGA floating point acceleration for High Performance Computing (Abstract)

John D. Cappello , Optimal Design, Inc., Sewell, NJ
Dave Strenski , Cray, Inc., Ypsilanti, Michigan
pp. 160-167

Sparse matrix-vector multiply on the Texas Instruments C6678 Digital Signal Processor (Abstract)

Yang Gao , Department of Computer Science and Engineering, University of South Carolina, Columbia, SC 29208, USA
Jason D. Bakos , Department of Computer Science and Engineering, University of South Carolina, Columbia, SC 29208, USA
pp. 168-174

Transforming a linear algebra core to an FFT accelerator (Abstract)

Ardavan Pedram , Department of Electrical and Computer Engineering, The University of Texas at Austin
John McCalpin , Texas Advanced Computing Center, The University of Texas at Austin
Andreas Gerstlauer , Department of Electrical and Computer Engineering, The University of Texas at Austin
pp. 175-184

A real-time implementation of the Total Focusing Method for rapid and precise diagnostic in non destructive evaluation (Abstract)

Mickael Njiki , Institut d'Electronique Fondamentale Univ Paris-Sud, UMR8622, Orsay, F-91405, France
Abdelhafid Elouardi , Institut d'Electronique Fondamentale Univ Paris-Sud, UMR8622, Orsay, F-91405, France
Samir Bouaziz , Institut d'Electronique Fondamentale Univ Paris-Sud, UMR8622, Orsay, F-91405, France
Olivier Casula , CEA-LIST, F-91191 Gif-sur-Yvette, France
Olivier Roy , M2M-NDT, F-91940, Les Ulis Courtaboeuf, France
pp. 245-248

A distributed CPU-GPU framework for pairwise alignments on large-scale sequence datasets (Abstract)

Da Li , Dept. of Electrical and Computer Engineering, University of Missouri
Kittisak Sajjapongse , Dept. of Electrical and Computer Engineering, University of Missouri
Huan Truong , MU Informatics Institute, University of Missouri
Gavin Conant , MU Informatics Institute, University of Missouri
Michela Becchi , Dept. of Electrical and Computer Engineering, University of Missouri
pp. 329-338

Program (Abstract)

pp. 1-4

Standard deviation of CPI: A new metric to evaluate architectural time predictability (Abstract)

Wei Zhang , Department of Electrical and Computer Engineering, Virginia Commonwealth University
Yiqiang Ding , Department of Electrical and Computer Engineering, Virginia Commonwealth University
pp. 111-112

Accelerating the performance of stochastic encoding-based computations by sharing bits in consecutive bit streams (Abstract)

Peng Li , Department of Electrical and Computer Engineering, University of Minnesota, Twin Cities, Minneapolis, MN, USA, 55812
David J. Lilja , Department of Electrical and Computer Engineering, University of Minnesota, Twin Cities, Minneapolis, MN, USA, 55812
pp. 257-260

FPGA-based HPC application design for non-experts (Abstract)

David Uliana , Virginia Polytechnic Institute and State University, Blacksburg, VA 24061, USA
Krzysztof Kepa , Virginia Polytechnic Institute and State University, Blacksburg, VA 24061, USA
Peter Athanas , Virginia Polytechnic Institute and State University, Blacksburg, VA 24061, USA
pp. 261-264

Incorporating temperature-leakage interdependency into dynamic voltage scaling for real-time systems (Abstract)

Junjun Gu , Altera Corporation 101 Innovation Drive, San Jose, CA 95134
Gang Qu , Electrical and Computer Engineering Department and Institute for Systems Research, University of Maryland, College Park, MD 20742
pp. 289-296

Hybrid SPM-cache architectures to achieve high time predictability and performance (Abstract)

Wei Zhang , Department of Electrical and Computer Engineering, Virginia Commonwealth University
Yiqiang Ding , Department of Electrical and Computer Engineering, Virginia Commonwealth University
pp. 297-304
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