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2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors (2011)
Santa Monica, CA
Sept. 11, 2011 to Sept. 14, 2011
ISBN: 978-1-4577-1291-3
TABLE OF CONTENTS
Papers

Table of contents (PDF)

pp. v-vii

[Front cover] (PDF)

pp. c1
Papers

More than 50 years of parallel processing and still no easy path to speedup (PDF)

M. Flynn , Electr. Eng., Stanford Univ., Stanford, CA, USA
pp. 4

External referees (PDF)

pp. xii-xiii

Program Committee (PDF)

pp. x-xi

Architectures for Green routers (PDF)

V. K. Prasanna , Univ. of Southern California, Los Angeles, CA, USA
pp. 5

CusComNet: A customisable network for reconfigurable heterogeneous clusters (Abstract)

S. Denholm , Dept. of Comput., Imperial Coll. London, London, UK
P. Pietzuch , Dept. of Comput., Imperial Coll. London, London, UK
Kuen Hung Tsoi , Dept. of Comput., Imperial Coll. London, London, UK
W. Luk , Dept. of Comput., Imperial Coll. London, London, UK
pp. 9-16

Address generation scheme for a coarse grain reconfigurable architecture (Abstract)

A. Hemani , Sch. of ICT, R. Inst. of Technol., Stockholm, Sweden
M. A. Shami , Sch. of ICT, R. Inst. of Technol., Stockholm, Sweden
pp. 17-24

Accelerating vision and navigation applications on a customizable platform (Abstract)

M. Vitanza , Dept. of Comput. Sci., Univ. of California, Los Angeles, CA, USA
G. Reinman , Dept. of Comput. Sci., Univ. of California, Los Angeles, CA, USA
B. Grigorian , Dept. of Comput. Sci., Univ. of California, Los Angeles, CA, USA
J. Cong , Dept. of Comput. Sci., Univ. of California, Los Angeles, CA, USA
pp. 25-32

A high-performance, low-power linear algebra core (Abstract)

A. Pedram , Dept. of Electr. & Comput. Eng., Univ. of Texas at Austin, Austin, TX, USA
A. Gerstlauer , Dept. of Electr. & Comput. Eng., Univ. of Texas at Austin, Austin, TX, USA
R. A. Geijn , Dept. of Comput. Sci., Univ. of Texas at Austin, Austin, TX, USA
pp. 35-42

A decimal floating-point fused multiply-add unit with a novel decimal leading-zero anticipator (Abstract)

M. J. Schulte , Res. & Adv. Dev. Labs., Adv. Micro Devices, Inc., Austin, TX, USA
pp. 43-50

Longest Prefix Match and updates in Range Tries (Abstract)

S. H. Katamaneni , Comput. Eng., Tech. Univ. Delft, Delft, Netherlands
I. Sourdis , Comput. Sci. & Eng., Chalmers Univ. of Technol., Gothenburg, Sweden
pp. 51-58

Low-cost hardware profiling of run-time and energy in FPGA embedded processors (Abstract)

M. Aldham , ECE Dept., Univ. of Toronto, Toronto, ON, Canada
J. Anderson , ECE Dept., Univ. of Toronto, Toronto, ON, Canada
S. Brown , ECE Dept., Univ. of Toronto, Toronto, ON, Canada
A. Canis , ECE Dept., Univ. of Toronto, Toronto, ON, Canada
pp. 61-68

TimeTrial: A low-impact performance profiler for streaming data applications (Abstract)

R. D. Chamberlain , Dept. of Comput. Sci. & Eng., Washington Univ. in St. Louis, St. Louis, MO, USA
J. D. Buhler , Dept. of Comput. Sci. & Eng., Washington Univ. in St. Louis, St. Louis, MO, USA
E. F. B. Shands , Dept. of Comput. Sci. & Eng., Washington Univ. in St. Louis, St. Louis, MO, USA
J. M. Lancaster , Dept. of Comput. Sci. & Eng., Washington Univ. in St. Louis, St. Louis, MO, USA
pp. 69-76

System-level design space exploration for dedicated heterogeneous multi-processor systems (Abstract)

L. Pomante , Center of Excellence DEWS, Univ. degli Studi dell'Aquila, Italy
pp. 79-86

Decentralized dynamic resource management support for massively parallel processor arrays (Abstract)

F. Hannig , Dept. of Comput. Sci., Univ. of Erlangen-Nuremberg, Nuremberg, Germany
A. Narovlyanskyy , Dept. of Comput. Sci., Univ. of Erlangen-Nuremberg, Nuremberg, Germany
V. Lari , Dept. of Comput. Sci., Univ. of Erlangen-Nuremberg, Nuremberg, Germany
J. Teich , Dept. of Comput. Sci., Univ. of Erlangen-Nuremberg, Nuremberg, Germany
pp. 87-94

Hybrid data structure for IP lookup in virtual routers using FPGAs (Abstract)

O. Erdem , Electr. & Electron. Eng., Middle East Tech. Univ., Ankara, Turkey
V. K. Prasanna , Ming Hsieh Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
H. Le , Ming Hsieh Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
C. F. Bazlamacci , Electr. & Electron. Eng., Middle East Tech. Univ., Ankara, Turkey
pp. 95-102

An area-Efficient LDPC decoder for multi-standard with conflict resolution (Abstract)

Yunlong Ge , State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
Changsheng Zhou , State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
Xiaoyang Zeng , State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
Xubin Chen , State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
Yun Chen , State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
pp. 105-112

High-throughput Contention-Free concurrent interleaver architecture for multi-standard turbo decoder (Abstract)

Guohui Wang , Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA
Yuanbin Guo , Wireless R&D, Futurewei Technol., Plano, TX, USA
Yang Sun , Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA
J. R. Cavallaro , Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA
pp. 113-121

Energy-efficient floating-point arithmetic for software-defined radio architectures (Abstract)

S. Z. Gilani , Dept. of Electr. & Comput. Eng., Univ. of Wisconsin - Madison, Madison, WI, USA
M. Schulte , Res. & Adv. Dev. Labs., Adv. Micro Devices, USA
Nam Sung Kim , Dept. of Electr. & Comput. Eng., Univ. of Wisconsin - Madison, Madison, WI, USA
pp. 122-129

On the performance of GPU public-key cryptography (Abstract)

S. Neves , Dept. of Inf. Eng., Univ. of Coimbra, Coimbra, Portugal
F. Araujo , Dept. of Inf. Eng., Univ. of Coimbra, Coimbra, Portugal
pp. 133-140

Exploiting structural redundancy of SIMD accelerators for their built-in self-testing/diagnosis and reconfiguration (Abstract)

A. Grasset , Thales Res. & Technol., Palaiseau, France
S. Yehia , Thales Res. & Technol., Palaiseau, France
D. Bertozzi , Univ. of Ferrara, Ferrara, Italy
A. Strano , Univ. of Ferrara, Ferrara, Italy
pp. 141-148

Accelerating the photon mapping algorithm and its hardware implementation (Abstract)

M. Ercegovac , Dept. of Comput. Sci., Univ. of California, Los Angeles, CA, USA
Seung hyun Pan , Dept. of Comput. Sci., Univ. of California, Los Angeles, CA, USA
S. Singh , Dept. of Comput. Sci., Univ. of California, Los Angeles, CA, USA
pp. 149-157

A low power fault-tolerance architecture for the kernel density estimation based image segmentation algorithm (Abstract)

D. J. Lilja , Dept. of Electr. & Comput. Eng., Univ. of Minnesota, Minneapolis, MN, USA
Peng Li , Dept. of Electr. & Comput. Eng., Univ. of Minnesota, Minneapolis, MN, USA
pp. 161-168

Instruction set extension for high throughput disparity estimation in stereo image processing (Abstract)

C. Banz , Inst. of Microelectron. Syst., Leibniz Univ. Hannover, Hannover, Germany
H. Blume , Inst. of Microelectron. Syst., Leibniz Univ. Hannover, Hannover, Germany
C. Dolar , Inst. of Microelectron. Syst., Leibniz Univ. Hannover, Hannover, Germany
F. Cholewa , Inst. of Microelectron. Syst., Leibniz Univ. Hannover, Hannover, Germany
pp. 169-175

Low energy motion estimation via selective aproximations (Abstract)

Y. Emre , Sch. of Electr., Comput. & Energy Eng., Arizona State Univ., Tempe, AZ, USA
C. Chakrabarti , Sch. of Electr., Comput. & Energy Eng., Arizona State Univ., Tempe, AZ, USA
pp. 176-183

An FPGA architecture for solving the Table Maker's Dilemma (Abstract)

J.-M Muller , Lab. LIP, UCBL, Lyon, France
B. Pasca , Lab. LIP, UCBL, Lyon, France
F. de Dinechin , Lab. LIP, UCBL, Lyon, France
A. Plesco , Lab. LIP, UCBL, Lyon, France
pp. 187-194

Next-generation massively parallel short-read mapping on FPGAs (Abstract)

T. B. Preusser , Dept. of Comput. Sci., Tech. Univ. Dresden, Dresden, Germany
O. Knodel , Dept. of Comput. Sci., Tech. Univ. Dresden, Dresden, Germany
R. G. Spallek , Dept. of Comput. Sci., Tech. Univ. Dresden, Dresden, Germany
pp. 195-201

An FPGA-based real-time nonuniformity correction system for Infrared Focal Plane Arrays (Abstract)

M. Figueroa , Dept. of Electr. Eng., Univ. of Concepcion, Concepcion, Chile
G. Carvajal , Dept. of Electr. Eng., Univ. of Concepcion, Concepcion, Chile
R. Redlich , Dept. of Electr. Eng., Univ. of Concepcion, Concepcion, Chile
pp. 202-208

Efficient custom instruction enumeration for extensible processors (Abstract)

Chenglong Xiao , Irisa, Univ. of Rennes I, France
E. Casseau , Irisa, Univ. of Rennes I, France
pp. 211-214

IP-XACT extensions for Reconfigurable Computing (Abstract)

V. M. Sima , Comput. Eng. Lab., Delft Univ. of Technol., Delft, Netherlands
S. van Haastregt , LIACS, Leiden Univ., Leiden, Netherlands
B. Kienhuis , LIACS, Leiden Univ., Leiden, Netherlands
K. Bertels , Comput. Eng. Lab., Delft Univ. of Technol., Delft, Netherlands
R. Nane , Comput. Eng. Lab., Delft Univ. of Technol., Delft, Netherlands
T. Stefanov , LIACS, Leiden Univ., Leiden, Netherlands
pp. 215-218

An integrated development toolset and implementation methodology for partially reconfigurable system-on-chips (Abstract)

A. Jara-Berrocal , Dept. of Electr. & Comput. Eng., Univ. of Florida, Gainesville, FL, USA
A. Gordon-Ross , Dept. of Electr. & Comput. Eng., Univ. of Florida, Gainesville, FL, USA
pp. 219-222

Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler (Abstract)

T. Beisel , Paderborn Center for Parallel Comput., Univ. of Paderborn, Paderborn, Germany
A. Brinkmann , Paderborn Center for Parallel Comput., Univ. of Paderborn, Paderborn, Germany
C. Plessl , Paderborn Center for Parallel Comput., Univ. of Paderborn, Paderborn, Germany
T. Wiersema , Paderborn Center for Parallel Comput., Univ. of Paderborn, Paderborn, Germany
pp. 223-226

Optimal design-space exploration of streaming applications (Abstract)

S. Padmanabhan , Dept. of Comput. Sci. & Eng., Washington Univ. in St. Louis, St. Louis, MO, USA
R. D. Chamberlain , Dept. of Comput. Sci. & Eng., Washington Univ. in St. Louis, St. Louis, MO, USA
Yixin Chen , Dept. of Comput. Sci. & Eng., Washington Univ. in St. Louis, St. Louis, MO, USA
pp. 227-230

Stack data management for Limited Local Memory (LLM) multi-core processors (Abstract)

A. Shrivastava , Compiler Microarchitecture Lab., USA
Ke Bai , Compiler Microarchitecture Lab., USA
S. Kudchadker , Compiler Microarchitecture Lab., USA
pp. 231-234

An energy efficient adaptive event detection scheme for wireless sensor network (Abstract)

Zheng Zhou , Dept. of Electr. & Comput. Eng., Univ. of Maryland, College Park, MD, USA
Gang Qu , Dept. of Electr. & Comput. Eng., Univ. of Maryland, College Park, MD, USA
pp. 235-238

Architecture model for approximate tandem repeat detection (Abstract)

M. Lexa , Fac. of Inf., Masaryk Univ., Brno, Czech Republic
T. Martinek , Fac. of Inf. Technol., Brno Univ. of Technol., Brno, Czech Republic
pp. 239-242

Design of a high performance FPGA based fault injector for real-time safety-critical systems (Abstract)

M. Miklo , Charles L. Brown Dept. of Comput. Eng., Univ. of Virginia, Charlottesville, VA, USA
R. D. Williams , Charles L. Brown Dept. of Comput. Eng., Univ. of Virginia, Charlottesville, VA, USA
C. R. Elks , Charles L. Brown Dept. of Comput. Eng., Univ. of Virginia, Charlottesville, VA, USA
pp. 243-246

Domain-specific processor with 3D integration for medical image processing (Abstract)

Bingjun Xiao , Comput. Sci. Dept., Univ. of California, Los Angeles, CA, USA
K. Guruaj , Comput. Sci. Dept., Univ. of California, Los Angeles, CA, USA
Yi Zou , Comput. Sci. Dept., Univ. of California, Los Angeles, CA, USA
Sen Li , Comput. Sci. Dept., Univ. of California, Los Angeles, CA, USA
Muhuan Huang , Comput. Sci. Dept., Univ. of California, Los Angeles, CA, USA
J. Cong , Comput. Sci. Dept., Univ. of California, Los Angeles, CA, USA
pp. 247-250

A parallel k-partition method to perform Montgomery Multiplication (Abstract)

J. C. Neto , Dept. of Comput. & Digital Syst. Eng., Univ. of Sao Paulo, Sao Paulo, Brazil
W. V. Ruggiero , Dept. of Comput. & Digital Syst. Eng., Univ. of Sao Paulo, Sao Paulo, Brazil
A. F. Tenca , Synopsys, Inc., OR, USA
pp. 251-254

A Residue Logarithmic Number System ALU using interpolation and cotransformation (Abstract)

V. Paliouras , Electr. & Comput. Eng., Univ. of Patras, Rio, Greece
M. G. Arnold , Comput. Sci. & Eng., Lehigh Univ., Bethlehem, PA, USA
I. Kouretas , Electr. & Comput. Eng., Univ. of Patras, Rio, Greece
pp. 255-258

Design and implementation of a belief propagation detector for sparse channels (Abstract)

A. G. Klein , Dept. of Electr. & Comput. Eng., Worcester Polytech. Inst., Worcester, MA, USA
Kai Zhang , Dept. of Electr. & Comput. Eng., Worcester Polytech. Inst., Worcester, MA, USA
Yanjie Peng , Dept. of Electr. & Comput. Eng., Worcester Polytech. Inst., Worcester, MA, USA
Xinming Huang , Dept. of Electr. & Comput. Eng., Worcester Polytech. Inst., Worcester, MA, USA
pp. 259-262

Author index (PDF)

pp. 263-264
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