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ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors (2010)
Rennes France
July 7, 2010 to July 9, 2010
ISSN: 1063-6268
ISBN: 978-1-4244-6966-6
TABLE OF CONTENTS

Convergence of design and fabrication technologies, a key enabler for HW-SW integration (PDF)

Ahmed A. Jerraya , CEA-LETI, 17 rue des Martyrs 38054 Grenoble cedex 9, France
pp. 3

The light at the end of the CMOS tunnel (PDF)

Sani R. Nassif , IBM Research, 11501 Burnet Rd., Austin, TX 78757
pp. 4-9

Dynamic code mapping for limited local memory systems (PDF)

Seung chul Jung , Arizona State University, Compiler Microarchitecture Lab, Tempe, AZ 85281, USA
Aviral Shrivastava , Arizona State University, Compiler Microarchitecture Lab, Tempe, AZ 85281, USA
Ke Bai , Arizona State University, Compiler Microarchitecture Lab, Tempe, AZ 85281, USA
pp. 13-20

Design of an Automatic Target Recognition algorithm on the IBM Cell Broadband Engine (PDF)

Weijia Che , Faculty of Computer Science and Engineering, Arizona State University, Tempe, AZ 85287
Karam S. Chatha , Faculty of Computer Science and Engineering, Arizona State University, Tempe, AZ 85287
pp. 21-28

Highly efficient mapping of the Smith-Waterman algorithm on CUDA-compatible GPUs (PDF)

Keisuke Dohi , Dept. of Computer and Information Sciences, Nagasaki University, Nagasaki, Japan
Khaled Benkridt , School of Engineering, King's Buildings., The University of Edinburgh, Edinburgh, United Kingdom
Cheng Ling , School of Engineering, King's Buildings., The University of Edinburgh, Edinburgh, United Kingdom
Tsuyoshi Hamada , Dept. of Computer and Information Sciences, Nagasaki University, Nagasaki, Japan
Yuichiro Shibata , Dept. of Computer and Information Sciences, Nagasaki University, Nagasaki, Japan
pp. 29-36

ImpEDE: A multidimensional design-space exploration framework for biomedical-implant processors (PDF)

Dhara Dave , Computer Engineering Lab, Delft University of Technology, P. O. Box 5031, 2600 GA Delft, The Netherlands
Christos Strydis , Computer Engineering Lab, Delft University of Technology, P. O. Box 5031, 2600 GA Delft, The Netherlands
Georgi N. Gaydadjiev , Computer Engineering Lab, Delft University of Technology, P. O. Box 5031, 2600 GA Delft, The Netherlands
pp. 39-46

Design space exploration of parametric pipelined designs (PDF)

Adrien Le Masle , Department of Computing Imperial College London, UK
Wayne Luk , Department of Computing Imperial College London, UK
pp. 47-54

Design space exploration for an embedded processor with flexible datapath interconnect (PDF)

Tung Thanh Hoang , VLSI Research Group, Department of Computer Science and Engineering Chalmers University of Technology, SE-412 96 Gothenburg, Sweden
Ulf Jalmbrant , VLSI Research Group, Department of Computer Science and Engineering Chalmers University of Technology, SE-412 96 Gothenburg, Sweden
Erik der Hagopian , VLSI Research Group, Department of Computer Science and Engineering Chalmers University of Technology, SE-412 96 Gothenburg, Sweden
Kasyab P. Subramaniyan , VLSI Research Group, Department of Computer Science and Engineering Chalmers University of Technology, SE-412 96 Gothenburg, Sweden
Magnus Sjalander , VLSI Research Group, Department of Computer Science and Engineering Chalmers University of Technology, SE-412 96 Gothenburg, Sweden
Per Larsson-Edefors , VLSI Research Group, Department of Computer Science and Engineering Chalmers University of Technology, SE-412 96 Gothenburg, Sweden
pp. 55-62

Using shared library interposing for transparent application acceleration in systems with heterogeneous hardware accelerators (PDF)

Tobias Beisel , Paderborn Center for Parallel Computing, University of Paderborn
Manuel Niekamp , Paderborn Center for Parallel Computing, University of Paderborn
Christian Plessl , Paderborn Center for Parallel Computing, University of Paderborn
pp. 65-72

Enhancing performance of network-on-chip architectures with millimeter-wave wireless interconnects (PDF)

Sujay Deb , School of Electrical Engineering and Computer Science, Washington State University, USA
Amlan Ganguly , School of Electrical Engineering and Computer Science, Washington State University, USA
Kevin Chang , School of Electrical Engineering and Computer Science, Washington State University, USA
Partha Pande , School of Electrical Engineering and Computer Science, Washington State University, USA
Benjamin Beizer , School of Electrical Engineering and Computer Science, Washington State University, USA
Deuk Heo , School of Electrical Engineering and Computer Science, Washington State University, USA
pp. 73-80

A Bayesian network-based framework with Constraint Satisfaction Problem (CSP) formulations for FPGA system design (PDF)

Amelia W. Azman , School of ITEE, The University of Queensland, Australia
Abbas Bigdeli , School of ITEE, The University of Queensland, Australia
Yasir Mohd-Mustafah , School of ITEE, The University of Queensland, Australia
Morteza Biglari-Abhari , Department of Electrical & Computer Engineering, The University of Auckland, New Zealand
Brian C. Lovell , School of ITEE, The University of Queensland, Australia
pp. 81-88

An optimized NoC architecture for accelerating TSP kernels in breakpoint median problem (PDF)

Turbo Majumder , School of Electrical Engineering and Computer Science, Washington State University, USA
Souradip Sarkar , School of Electrical Engineering and Computer Science, Washington State University, USA
Partha Pande , School of Electrical Engineering and Computer Science, Washington State University, USA
Ananth Kalyanaraman , School of Electrical Engineering and Computer Science, Washington State University, USA
pp. 89-96

A formal specification of fault-tolerance in prospecting asteroid mission with Reactive Autonomie Systems Framework (PDF)

Heng Kuang , Concordia University, Montreal, Canada
Olga Ormandjieva , Concordia University, Montreal, Canada
Stan Klasa , Concordia University, Montreal, Canada
Jamal Bentahar , Concordia University, Montreal, Canada
pp. 99-106

Comparing the robustness of fault-tolerant enhancements when applied to lookup tables and random logic for nano-computing (PDF)

Yocheved Dotan , Dept. of Electrical and Computer Eng., Ruppin Academic Center, Ruppin, Israel
Orgad Chen , Dept. of Electrical and Computer Eng., Ruppin Academic Center, Ruppin, Israel
Gil Katz , Dept. of Electrical and Computer Eng., Ruppin Academic Center, Ruppin, Israel
pp. 107-114

Dependability analysis of a countermeasure against fault attacks by means of laser shots onto a SRAM-based FPGA (PDF)

G. Canivet , TIMA Laboratory (Grenoble INP, UJF, CNRS) - 46 Avenue Félix Viallet - 38031 Grenoble - France
P. Maistri , TIMA Laboratory (Grenoble INP, UJF, CNRS) - 46 Avenue Félix Viallet - 38031 Grenoble - France
R. Leveugle , TIMA Laboratory (Grenoble INP, UJF, CNRS) - 46 Avenue Félix Viallet - 38031 Grenoble - France
F. Valette , DGA / CELAR - 35171 Bruz Cedex- France
J. Clediere , CESTI / CEA-LETI, Minatec - 17 Avenue des Martyrs - 38054 Grenoble Cedex 9- France
M. Renaudin , Tiempo -110 Rue Blaise Pascal - 38330 Montbonnot Saint Martin- France
pp. 115-122

Modeling and synthesis of communication subsystems for loop accelerator pipelines (PDF)

Hritam Dutta , University ofErlangen-Nuremberg, Germany
Frank Hannig , University ofErlangen-Nuremberg, Germany
Moritz Schmid , University ofErlangen-Nuremberg, Germany
Joachim Keinert , Fraunhofer Institute for Integrated Circuits, Germany
pp. 125-132

Design of throughput-optimized arrays from recurrence abstractions (PDF)

Arpith C. Jacob , Department of Computer Science and Engineering, Washington University in St. Louis
Jeremy D. Buhler , Department of Computer Science and Engineering, Washington University in St. Louis
Roger D. Chamberlain , Department of Computer Science and Engineering, Washington University in St. Louis
pp. 133-140

A C++-embedded Domain-Specific Language for programming the MORA soft processor array (PDF)

W. Vanderbauwhede , Dept. of Computing Scienc, University of Glasgow, Glasgow, UK
M. Margala , Dept. of Electrical and Computer Engineering, University of Massachusetts at Lowell, Lowell, MA, USA
S. R. Chalamalasetti , Dept. of Electrical and Computer Engineering, University of Massachusetts at Lowell, Lowell, MA, USA
S. Purohit , Dept. of Electrical and Computer Engineering, University of Massachusetts at Lowell, Lowell, MA, USA
pp. 141-148

A forwarding-sensitive instruction scheduling approach to reduce register file constraints in VLIW architectures (PDF)

Guillermo Paya-Vaya , Institute of Microelectronic Systems, Leibniz Universität Hannover Appelstr. 4, 30167 Hannover (Germany)
Javier Martin-Langerwerf , Institute of Microelectronic Systems, Leibniz Universität Hannover Appelstr. 4, 30167 Hannover (Germany)
Holger Blume , Institute of Microelectronic Systems, Leibniz Universität Hannover Appelstr. 4, 30167 Hannover (Germany)
Peter Pirsch , Institute of Microelectronic Systems, Leibniz Universität Hannover Appelstr. 4, 30167 Hannover (Germany)
pp. 151-158

Dual-purpose custom instruction identification algorithm based on Particle Swarm Optimization (PDF)

Mehdi Kamal , School of Electrical and Computer Engineering, University of Tehran
Neda Kazemian Amiri , School of Electrical and Computer Engineering, University of Tehran
Arezoo Kamran , School of Electrical and Computer Engineering, University of Tehran
Seyyed Alireza Hoseini , School of Electrical and Computer Engineering, University of Tehran
Masoud Dehyadegari , School of Electrical and Computer Engineering, University of Tehran
Hamid Noori , School of Electrical and Computer Engineering, University of Tehran
pp. 159-166

Combined scheduling and instruction selection for processors with reconfigurable cell fabric (PDF)

Antoine Floch , University of Rennes I, Irisa, Inria, France
Christophe Wolinski , University of Rennes I, Irisa, Inria, France
Krzysztof Kuchcinski , Dept. of Computer Science, Lund University, Sweden
pp. 167-174

Completeness of automatically generated instruction selectors (PDF)

Florian Brandner , COMPSYS, LIP, ENS de Lyon UMR 5668 CNRS - ENS de Lyon - UCB Lyon - Inria Lyon, France
pp. 175-182

Implementation of binary edwards curves for very-constrained devices (PDF)

Unal Kocabas , Katholieke Universiteit Leuven, ESAT/SCD-COSIC, Kasteelpark Arenberg 10, B-3001 Leuven-Heverlee, Belgium
Junfeng Fan , Katholieke Universiteit Leuven, ESAT/SCD-COSIC, Kasteelpark Arenberg 10, B-3001 Leuven-Heverlee, Belgium
Ingrid Verbauwhede , Katholieke Universiteit Leuven, ESAT/SCD-COSIC, Kasteelpark Arenberg 10, B-3001 Leuven-Heverlee, Belgium
pp. 185-191

Elliptic Curve point multiplication on GPUs (PDF)

Samuel Antao , Instituto Superior Técnico/INESC-ID, Technical University of Lisbon, Lisbon, Portugal
Jean-Claude Bajard , Laboratoire d'Informatique de Paris 6, Université Pierre et Marie Curie, Paris, France
Leonel Sousa , Instituto Superior Técnico/INESC-ID, Technical University of Lisbon, Lisbon, Portugal
pp. 192-199

Newton-Raphson algorithms for floating-point division using an FMA (PDF)

Nicolas Louvet , UCBL, LIP (CNRS, ENS de Lyon, INRIA, UCBL), Université de Lyon
Jean-Michel Muller , CNRS, LIP (CNRS, ENS de Lyon, INRIA, UCBL), Université de Lyon
Adrien Panhaleux , École Normale Supérieure de Lyon, Université de Lyon, LIP (CNRS, ENS de Lyon, INRIA, UCBL)
pp. 200-207

Automatic generation of polynomial-based hardware architectures for function evaluation (PDF)

Florent de Dinechin , LIP (CNRS/INRIA/ENS-Lyon/UCBL), Université de Lyon
Mioara Joldes , LIP (CNRS/INRIA/ENS-Lyon/UCBL), Université de Lyon
Bogdan Pasca , LIP (CNRS/INRIA/ENS-Lyon/UCBL), Université de Lyon
pp. 216-222

A fully-overlapped multi-mode QC-LDPC decoder architecture for mobile WiMAX applications (PDF)

Bo Xiang , State Key Lab. of ASIC and System, Fudan University, Shanghai, China
Dan Bao , State Key Lab. of ASIC and System, Fudan University, Shanghai, China
Shuangqu Huang , State Key Lab. of ASIC and System, Fudan University, Shanghai, China
Xiaoyang Zeng , State Key Lab. of ASIC and System, Fudan University, Shanghai, China
pp. 225-232

High parallel variation Banyan network based permutation network for reconfigurable LDPC decoder (PDF)

Xiao Peng , The Graduate School of Information, Production and Systems Waseda University, Kitakyushu, Japan
Zhixiang Chen , The Graduate School of Information, Production and Systems Waseda University, Kitakyushu, Japan
Xiongxin Zhao , The Graduate School of Information, Production and Systems Waseda University, Kitakyushu, Japan
Fumiaki Maehara , The Graduate School of Information, Production and Systems Waseda University, Kitakyushu, Japan
Satoshi Goto , The Graduate School of Information, Production and Systems Waseda University, Kitakyushu, Japan
pp. 233-238

A high efficient memory architecture for H.264/AVC motion compensation (PDF)

Chunshu Li , Institute of VLSI Design, Zhejiang University, Hangzhou, China
Kai Huang , Institute of VLSI Design, Zhejiang University, Hangzhou, China
Xiaolang Yan , Institute of VLSI Design, Zhejiang University, Hangzhou, China
Jiong Feng , Soc Design Group, C-sky Microsystem Corporation, Hangzhou, China
De Ma , Soc Design Group, C-sky Microsystem Corporation, Hangzhou, China
Haitong Ge , Soc Design Group, C-sky Microsystem Corporation, Hangzhou, China
pp. 239-245

FPGA-based lossless compressors of floating-point data streams to enhance memory bandwidth (PDF)

Kazuya Katahira , Graduate School of Information Sciences, Tohoku University, 6-6-01 Aramaki Aza Aoba, Sendai, 980-8579, Japan
Kentaro Sano , Graduate School of Information Sciences, Tohoku University, 6-6-01 Aramaki Aza Aoba, Sendai, 980-8579, Japan
Satoru Yamamoto , Graduate School of Information Sciences, Tohoku University, 6-6-01 Aramaki Aza Aoba, Sendai, 980-8579, Japan
pp. 246-253

Power dissipation challenges in multicore floating-point units (PDF)

Wei Liu , Dept. of Informatics & Mathematical Modelling, Technical University of Denmark, Kongens Lyngby, Denmark
Alberto Nannarelli , Dept. of Informatics & Mathematical Modelling, Technical University of Denmark, Kongens Lyngby, Denmark
pp. 257-264

On energy efficiency of reconfigurable systems with run-time partial reconfiguration (PDF)

Shaoshan Liu , EECS, University of California, Irvine
Richard Neil Pittman , Microsoft Research, Redmond
Alessandro Form , Microsoft Research, Redmond
Jean-Luc Gaudiot , EECS, University of California, Irvine
pp. 265-272

A GALS FFT processor with clock modulation for low-EMI applications (PDF)

Xin Fan , IHP Microelectronics Im Technologiepark 25, Frankfurt (Oder), 15236, Germany
Milos Krstic , IHP Microelectronics Im Technologiepark 25, Frankfurt (Oder), 15236, Germany
Christoph Wolf , IHP Microelectronics Im Technologiepark 25, Frankfurt (Oder), 15236, Germany
Eckhard Grass , IHP Microelectronics Im Technologiepark 25, Frankfurt (Oder), 15236, Germany
pp. 273-278

Hardware-assisted middleware: Acceleration of garbage collection operations (PDF)

Jie Tang , Beijing Institute of Technology
Shaoshan Liu , University of California, Irvine
Zhimin Gu , Beijing Institute of Technology
Xiao-Feng Li , Intel China Research Center, Beijing
Jean-Luc Gaudiot , University of California, Irvine
pp. 281-284

Flexible hardware/software co-design for scalable elliptic curve cryptography for low-resource applications (PDF)

M. N. Hassan , Department of Electronic and Electrical Engineering, University of Sheffield, Sheffield, S1 3JD, UK
M. Benaissa , Department of Electronic and Electrical Engineering, University of Sheffield, Sheffield, S1 3JD, UK
A. Kanakis , Department of Electronic and Electrical Engineering, University of Sheffield, Sheffield, S1 3JD, UK
pp. 285-288

An efficient computation model for coarse grained reconfigurable architectures and its applications to a reconfigurable computer (PDF)

Oguzhan Atak , Department of Electrical and Electronics Engineering, Bilkent University, Ankara, Turkey
Abdullah Atalar , Department of Electrical and Electronics Engineering, Bilkent University, Ankara, Turkey
pp. 289-292

Potential of using block floating point arithmetic in ASIP-based GNSS-receivers (PDF)

E. Tasdemir , Chair of Electrical Engineering and Computer Systems, RWTH Aachen University, Schinkelstr. 2, 52062 Aachen, Germany
G. Kappen , Chair of Electrical Engineering and Computer Systems, RWTH Aachen University, Schinkelstr. 2, 52062 Aachen, Germany
T. G. Noll , Chair of Electrical Engineering and Computer Systems, RWTH Aachen University, Schinkelstr. 2, 52062 Aachen, Germany
pp. 293-296

Area optimized H.264 Intra prediction architecture for 1080p HD resolution (PDF)

Jimit Shah , CEDT, Indian Institute of Science
K. S. Raghunandan , CEDT, Indian Institute of Science
Kuruvilla Varghese , CEDT, Indian Institute of Science
pp. 297-300

Memoryless RNS-to-binary converters for the {2n+1 - 1, 2n, 2n - 1} moduli set (PDF)

Kazeem Alagbe Gbolagade , CE Lab, Delft University of Technology, The Netherlands
George Razvan Voicu , CE Lab, Delft University of Technology, The Netherlands
Sorin Dan Cotofana , CE Lab, Delft University of Technology, The Netherlands
pp. 301-304

A pipelined camellia architecture for compact hardware implementation (PDF)

Elif Bilge Kavun , Department of Cryptography, Institute of Applied Mathematics, METU, Ankara, Turkey
Tolga Yalcin , Department of Cryptography, Institute of Applied Mathematics, METU, Ankara, Turkey
pp. 305-308

General-purpose FPGA platform for efficient encryption and hashing (PDF)

Jakub Szefer , Department of Electrical Engineering, Princeton University, Princeton, NJ, USA
Yu-Yuan Chen , Department of Electrical Engineering, Princeton University, Princeton, NJ, USA
Ruby B. Lee , Department of Electrical Engineering, Princeton University, Princeton, NJ, USA
pp. 309-312

A compact FPGA-based architecture for elliptic curve cryptography over prime fields (PDF)

Jo Vliegen , ESAT, SCD/COSIC, Katholieke Universiteit Leuven, 3001 Leuven, Belgium
Nele Mentens , ESAT, SCD/COSIC, Katholieke Universiteit Leuven, 3001 Leuven, Belgium
Jan Genoe , IWT, ACRO/ES&S, Katholieke Hogeschool Diepenbeek, 3590 Diepenbeek, Belgium
An Braeken , IWT, Erasmushogeschool Brüssel, 1070 Anderlecht, Belgium
Serge Kubera , IWT, Erasmushogeschool Brüssel, 1070 Anderlecht, Belgium
Abdellah Touhafi , IWT, Erasmushogeschool Brüssel, 1070 Anderlecht, Belgium
Ingrid Verbauwhede , ESAT, SCD/COSIC, Katholieke Universiteit Leuven, 3001 Leuven, Belgium
pp. 313-316

Implementing decimal floating-point arithmetic through binary: Some suggestions (PDF)

Nicolas Brisebarre , CNRS, ENSL, INRI A, UCBL, Univ. Lyon, Lab. LIP (UMR 5668), École Normale Supérieure de Lyon, LIP, 46 allée d'Italie, 69364 Lyon Cedex 07, France
Nicolas Louvet , CNRS, ENSL, INRI A, UCBL, Univ. Lyon, Lab. LIP (UMR 5668), École Normale Supérieure de Lyon, LIP, 46 allée d'Italie, 69364 Lyon Cedex 07, France
Erik Martin-Dorel , CNRS, ENSL, INRI A, UCBL, Univ. Lyon, Lab. LIP (UMR 5668), École Normale Supérieure de Lyon, LIP, 46 allée d'Italie, 69364 Lyon Cedex 07, France
Jean-Michel Muller , CNRS, ENSL, INRI A, UCBL, Univ. Lyon, Lab. LIP (UMR 5668), École Normale Supérieure de Lyon, LIP, 46 allée d'Italie, 69364 Lyon Cedex 07, France
Adrien Panhaleux , CNRS, ENSL, INRI A, UCBL, Univ. Lyon, Lab. LIP (UMR 5668), École Normale Supérieure de Lyon, LIP, 46 allée d'Italie, 69364 Lyon Cedex 07, France
Milos D. Ercegovac , 4731H Boelter Hall, Computer Science Department, University of California at Los Angeles, Los Angeles, CA 90024, USA
pp. 317-320

A New approach in on-line task scheduling for reconfigurable computing systems (PDF)

Maisam Mansub Bassiri , Department of Electrical Engineering, Iran University of Science and Technology, Tehran, Iran
Hadi Shahriar Shahhoseini , Department of Electrical Engineering, Iran University of Science and Technology, Tehran, Iran
pp. 321-324

Exploring algorithmic trading in reconfigurable hardware (PDF)

Stephen Wray , Department of Computing Imperial College London London, United Kingdom
Wayne Luk , Department of Computing Imperial College London London, United Kingdom
Peter Pietzuch , Department of Computing Imperial College London London, United Kingdom
pp. 325-328

Optimizing DDR-SDRAM communications at C-level for automatically-generated hardware accelerators an experience with the Altera C2H HLS tool (PDF)

Christophe Alias , LIP, UMR 5668 CNRS — ENS Lyon — UCB Lyon — Inria, France
Alain Darte , LIP, UMR 5668 CNRS — ENS Lyon — UCB Lyon — Inria, France
Alexandra Plesco , LIP, UMR 5668 CNRS — ENS Lyon — UCB Lyon — Inria, France
pp. 329-332

Deadlock-avoidance for streaming applications with split-join structure: Two case studies (PDF)

Peng Li , Department of Computer Science and Engineering Washington Univeristy in St. Louis St. Louis, Missouri, United States
Kunal Agrawal , Department of Computer Science and Engineering Washington Univeristy in St. Louis St. Louis, Missouri, United States
Jeremy Buhler , Department of Computer Science and Engineering Washington Univeristy in St. Louis St. Louis, Missouri, United States
Roger D. Chamberlain , Department of Computer Science and Engineering Washington Univeristy in St. Louis St. Louis, Missouri, United States
Joseph M. Lancaster , Department of Computer Science and Engineering Washington Univeristy in St. Louis St. Louis, Missouri, United States
pp. 333-336

Customizing controller instruction sets for application-specific architectures (PDF)

Jian Li , School of Engineering Science, Simon Fraser University, Burnaby, British Columbia, Canada
David Dickin , School of Engineering Science, Simon Fraser University, Burnaby, British Columbia, Canada
Lesley Shannon , School of Engineering Science, Simon Fraser University, Burnaby, British Columbia, Canada
pp. 337-340

Loop transformations for interface-based hierarchies IN SDF graphs (PDF)

Jonathan Piat , IETR/INSA, UMR CNRS 6164, Image and Remote Sensing laboratory, F-35043 Rennes, France
Shuvra S. Bhattacharyya , Department of Electrical and Computer Engineering, University of Maryland, College Park, MD, 20742, USA
Michael Raulet , IETR/INSA, UMR CNRS 6164, Image and Remote Sensing laboratory, F-35043 Rennes, France
pp. 341-344

Code generation for hardware accelerated AES (PDF)

Raymond Manley , School of Computer Science and Statistics, Trinity College Dublin, Dublin, Ireland
Paul Magrath , School of Computer Science and Statistics, Trinity College Dublin, Dublin, Ireland
David Gregg , School of Computer Science and Statistics, Trinity College Dublin, Dublin, Ireland
pp. 345-348

Function flattening for lease-based, information-leak-free systems (Abstract)

Xun Li , Department of Computer Science, University of California, Santa Barbara, Santa Barbara, USA
Mohit Tiwari , Department of Computer Science, University of California, Santa Barbara, Santa Barbara, USA
Timothy Sherwood , Department of Computer Science, University of California, Santa Barbara, Santa Barbara, USA
Frederic T. Chong , Department of Computer Science, University of California, Santa Barbara, Santa Barbara, USA
pp. 349-352
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