2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors (2009)

Boston, MA, USA

July 7, 2009 to July 9, 2009

ISSN: 1063-6862

ISBN: 978-0-7695-3732-0

pp: 215-218

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASAP.2009.31

ABSTRACT

The Spectral Hash algorithm is one of the Round 1 candidates for the SHA-3 family, and is based on spectral arithmetic over a finite field, involving multidimensional discrete Fourier transformations over a finite field, data dependent permutations, Rubic-type rotations, and affine and nonlinear functions. The underlying mathematical structures and operations pose interesting and challenging tasks for computer architects and hardware designers to create fast, efficient, and compact ASIC and FPGA realizations. In this paper, we present an efficient hardware architecture for the full 512-bit hash computation using the spectral hash algorithm. We have created a pipelined implementation on a Xilinx Virtex-4 XC4VLX200-11 FPGA which yields 100 MHz and occupies 38,328 slices, generating a throughput of 51.2 Gbps. Our fully parallel synthesized implementation shows that the spectral hash algorithm is about 100 times faster than the fastest SHA-1 implementation, while requiring only about 13 times as many logic slices.

INDEX TERMS

FPGA, Cryptography, Hashing

CITATION

J. D. Villasenor, &. K. Koç and R. C. Cheung, "A High-Performance Hardware Architecture for Spectral Hash Algorithm,"

*2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors(ASAP)*, Boston, MA, USA, 2009, pp. 215-218.

doi:10.1109/ASAP.2009.31

CITATIONS