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2008 International Conference on Application-Specific Systems, Architectures and Processors (2008)
Leuven, Belgium
July 2, 2008 to July 4, 2008
ISBN: 978-1-4244-1897-8
pp: 245-250
Andres Garcia , Delft University of Technology, Computer Engineering, Mekelweg 4, 2628 CD, The Netherlands
Mladen Berekovic , Technical University Braunschweig, Hans-Sommer-Str. 66, 38106, Germany
Tom Vander Aa , IMEC vzw, NES, Kapeldreef 75, B-3001 Leuven, Belgium
ABSTRACT
Coarse-Grained reconfigurable architectures are emerging as potential candidates to meet the high performance, power efficiency and flexibility needed by embedded systems. ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its DRESC compiler offer a very promising platform for designing embedded systems targeted for different application domains. We present a procedure for mapping the widely used AES cryptographic algorithm on ADRES. A detailed explanation is shown for each of the optimizations performed in order to make better use of instruction and loop parallelism. A new intrinsic function set is proposed for speeding up the processing of the AES algorithm. The obtained simulation results are compared with experiments done on the widely known Texas Instruments DSP: TI C64x, which is considered state-of-the-art for embedded systems. Our results show that ADRES outperforms TI C64x DSP, executing the AES algorithm in one fourth of the cycles.
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CITATION

T. Vander Aa, M. Berekovic and A. Garcia, "Mapping of the AES cryptographic algorithm on a Coarse-Grain reconfigurable array processor," 2008 International Conference on Application-Specific Systems, Architectures and Processors(ASAP), Leuven, Belgium, 2008, pp. 245-250.
doi:10.1109/ASAP.2008.4580186
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