2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP) (2007)
Montreal, QC, Canada
July 9, 2007 to July 11, 2007
Jerome Dubois , Laboratoire LE2I -UMR CNRS 5158, Université de Bourgogne, 21078 Dijon Cedex -France
Dominique Ginhac , Laboratoire LE2I -UMR CNRS 5158, Université de Bourgogne, 21078 Dijon Cedex -France
Michel Paindavoine , Laboratoire LE2I -UMR CNRS 5158, Université de Bourgogne, 21078 Dijon Cedex -France
A high speed Analog VLSI Image acquisition and pre-processing system is described in this paper. A 64×64 pixel retina is used to extract the magnitude and direction of spatial gradients from images. So, the sensor implements some lowlevel image processing in a massively parallel strategy in each pixel of the sensor. Spatial gradients, various convolutions as Sobel filter or Laplacian are described and implemented on the circuit. The retina implements in a massively parallel way, at pixel level, some various treatments based on a four-quadrants multipliers architecture. Each pixel includes a photodiode, an amplifier, two storage capacitors and an analog arithmetic unit. A maximal output frame rate of about 10 000 frames per second with only image acquisition and 2000 to 5000 frames per second with image processing is achieved in a 0.35 µm standard CMOS process. The retina provides address-event coded output on three asynchronous buses, one output is dedicated to the gradient and both other to the pixel values. A prototype based on this principle, has been designed. Simulation results from Mentor Graphics™software and AustriaMicrosystem Design kit are presented.
J. Dubois, M. Paindavoine and D. Ginhac, "A single-chip 10 000 frames/s CMOS sensor with in-situ 2D programmable image processing," 2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP), Montreal, QC, Canada, 2007, pp. 124-129.