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2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors (2006)
Steamboat Springs, Colorado, USA
Sept. 11, 2006 to Sept. 13, 2006
ISSN: 1063-6862
ISBN: 0-7695-2682-9
TABLE OF CONTENTS
Introduction

Program Committee (PDF)

pp. xiii
Session 1: Configurable Computing Machines (Invited)

Configurable Computing Platforms - Promises, Promises (Abstract)

Carl Ebeling , University of Washington
pp. 3-4
Session 2: Processing, Storage and Network On-Chip

Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip (PDF)

Patrick Schaumont , Virginia Tech.
Wei Qin , Boston University
Ingrid Verbauwhede , EE Dept. UCLA, CA and ESAT, K.U.Leuven, BE
pp. 15-18

The Molen FemtoJava Engine (Abstract)

Luigi Carro , UFRGS Porto Alegre, Brazil
Stephan Wong , TUDelft, The Netherlands
Julio C. B. Mattos , UFRGS Porto Alegre, Brazil
pp. 19-22

Minimum Cost for Channels and Registers in Processor Arrays by Avoiding Redundancy (Abstract)

Sebastian Siegel , Dresden University of Technology, Germany
Renate Merker , Dresden University of Technology, Germany
pp. 28-32

NoC Hot Spot minimization Using AntNet Dynamic Routing Algorithm (Abstract)

M. Daneshtalab , University of Tehran, Tehran, Iran
A. Afzali-Kusha , University of Tehran, Tehran, Iran
A. Sobhani , University of Tehran, Tehran, Iran
Z. Navabi , Northeastern University, Boston, U.S.A.
O. Fatemi , University of Tehran, Tehran, Iran
pp. 33-38
Session 3: Configurable Processors and Tools (Invited)

Recent Developments in Configurable and Extensible Processors (Abstract)

Grant Martin , Tensilica, Inc., Santa Clara, California
pp. 39-44

Software Configurable Processors (Abstract)

Jeffrey M. Arnold , Stretch, Inc., Mountain View, CA
pp. 45-49
Session 4: Parallel Connection Architectures

Fast Bit Compression and Expansion with Parallel Extract and Parallel Deposit Instructions (Abstract)

Ruby B. Lee , Princeton University, Princeton, NJ
Yedidya Hilewitz , Princeton University, Princeton, NJ
pp. 65-72

A Mesh-of-Trees Interconnection Network for Single-Chip Parallel Processing (Abstract)

Aydin O. Balkan , University of Maryland
Gang Qu , University of Maryland
Uzi Vishkin , University of Maryland
pp. 73-80

Reconfigurable Shuffle Network Design in LDPC Decoders (Abstract)

Jun Tang , University of Minnesota, Twin Cities, MN
Vishwas Sundaramurthy , Nokia Inc., Irving, TX
Tejas Bhatt , Nokia Inc., Irving, TX
pp. 81-86

2D-VLIW: An Architecture Based on the Geometry of Computation (Abstract)

Rodolfo Azevedo , State University of Campinas Institute of Computing, Brazil
Ricardo Santos , Dom Bosco Catholic University, Campo Grande, MS, Brazil
Guido Araujo , State University of Campinas Institute of Computing, Brazil
pp. 87-94
Session 5: Parallel Processing and Arithmetic

An Efficient Implementation of High-Accuracy Finite Difference Computing Engine on FPGAs (Abstract)

Chuan He , Texas A&M University, College Station, TX
Guan Qin , Texas A&M University, College Station, TX
Wei Zhao , Texas A&M University, College Station, TX
Mi Lu , Texas A&M University, College Station, TX
pp. 95-98

Performance Evaluation of a Novel Direct Table Lookup Method and Architecture with Application to 16-bit Integer Functions (Abstract)

D. W. Matula , Southern Methodist University
Alex Fit-Florea , Southern Methodist University
L. Li , Southern Methodist University
M. A. Thornton , Southern Methodist University
pp. 99-104

Design of Radix-4 SRT Dividers in 65 Nanometer CMOS Technology (Abstract)

Tung N. Pham , University of Texas at Austin
Earl E. Jr. Swartzlander , University of Texas at Austin
pp. 105-108

Describing Quantum Circuits with Systolic Arrays (Abstract)

Euripides Montagne , University of Central Florida, Orlando, FL
Aasavari Bhave , University of Central Florida, Orlando, FL
pp. 109-113

FPGA Implementation of Beamforming Receivers Based on MRC and NC-LMS for DS-CDMA System (Abstract)

Messaoud Ahmed-Ouameur , Universite du Qu?bec a Trois-Rivieres, Canada
Daniel Massicotte , Universite du Qu?bec a Trois-Rivieres, Canada
Elie H. Sarraf , Universite du Qu?bec a Trois-Rivieres, Canada
pp. 114-117

Low Complexity Design of High Speed Parallel Decision Feedback Equalizers (Abstract)

Keshab K. Parhi , University of Minnesota, Minneapolis, MN
Daesun Oh , University of Minnesota, Minneapolis, MN
pp. 118-124
Session 6: Arithmetic: Analysis and Implementation

Quantitative Analysis of Embedded FPGA-Architectures for Arithmetic (Abstract)

T. von Sydow , RWTH Aachen University, Germany
B. Neumann , RWTH Aachen University, Germany
H. Blume , RWTH Aachen University, Germany
T. G. Noll , RWTH Aachen University, Germany
pp. 125-131

A Cost Effective Pipelined Divider for Double Precision Floating Point Number (Abstract)

Jayanta Biswas , CAD Lab, Indian Institute of Science, Bangalore
Sandeep B. Singh , CAD Lab, Indian Institute of Science, Bangalore
S. K. Nandy , CAD Lab, Indian Institute of Science, Bangalore
pp. 132-137

A 64-bit Decimal Floating-Point Comparator (Abstract)

James E. Stine , Oklahoma State University
Ivan D. Castellanos , Oklahoma State University
pp. 138-144

Pipelined Range Reduction for Floating Point Numbers (Abstract)

Julio Villalba , University of Malaga
Javier Hormigo , University of Malaga
Francisco J. Jaime , University of Malaga
Emilio L. Zapata , University of Malaga
pp. 145-152
Session 7: 20th Anniversary Review-Array Processors (Invited)

Systolic FFT Processors: Past, Present and Future (Abstract)

Earl E. Jr. Swartzlander , University of Texas at Austin
pp. 153-158

From Bit Level Systolic Arrays to HDTV Processor Chips (Abstract)

Roger F Woods , Queen?s University Belfast, Belfast, N Ireland
John V McCanny , Queen?s University Belfast, Belfast, N Ireland
John G McWhirter , Qinetiq Ltd., St Andrews Rd Malvern Worcs. England
pp. 159-162

The UCSC Kestrel Application-Unspecific Processor (Abstract)

Richard Hughey , University of California, Santa Cruz, CA
Andrea Di Blas , University of California, Santa Cruz, CA
pp. 163-168

Multicore processors as Array Processors: Research Opportunities (Abstract)

Peter Cappello , University of California, Santa Barbara
pp. 169-172
Session 8: Analysis and Optimizations

Analysis of a Fully-Scalable Digital Fractional Clock Divider (Abstract)

Rainer G. Spallek , Technische Universitat Dresden, Germany
Thomas B. Preuber , Technische Universitat Dresden, Germany
pp. 173-177

Voltage Assignment and Loop Scheduling for Energy Minimization while Satisfying Timing Constraint with Guaranteed Probability (Abstract)

Qingfeng Zhuge , Hong Kong Polytechnic Univ., Hung Hom, Kowloon, Hongkong.
Chun Xue , Hong Kong Polytechnic Univ., Hung Hom, Kowloon, Hongkong.
Meikang Qiu , Hong Kong Polytechnic Univ., Hung Hom, Kowloon, Hongkong.
Meilin Liu , Hong Kong Polytechnic Univ., Hung Hom, Kowloon, Hongkong.
Edwin H.-M. Sha , Hong Kong Polytechnic Univ., Hung Hom, Kowloon, Hongkong.
Zili Shao , Hong Kong Polytechnic Univ., Hung Hom, Kowloon, Hongkong.
pp. 178-181

Parallel Processing Based Power Reduction in a 256 State Viterbi Decoder (Abstract)

Woo Hyung Lee , University of Michigan
Pinaki Mazumber , University of Michigan
pp. 182-185

Affine Nested Loop Programs and their Binary Parameterized Dataflow Graph Counterparts (Abstract)

Shuvra S. Bhattacharyya , University of Maryland
Ed F. Deprettere , Leiden University
Mainak Sen , University of Maryland
Todor Stefanov , Leiden University
pp. 186-190

Polyhedral Modeling and Analysis of Memory Access Profiles (Abstract)

Philippe Clauss , ICPS/LSIIT, Universite Louis Pasteur, Strasbourg, France
Benedicte Kenmei , ICPS/LSIIT, Universite Louis Pasteur, Strasbourg, France
pp. 191-198
Session 9: 20th Anniversary Review Optimizations and Applications (Invited)

Loop Transformation Methodologies for Array-Oriented Memory Management (Abstract)

F. Balasa , University of Illinois at Chicago, Chicago, U.S.A.
P.G. Kjeldsberg , Norwegian University of Science and Technology, Trondheim, Norway
A. Vandecappelle , IMEC vzw, Leuven, Belgium
F. Catthoor , IMEC vzw, Leuven, Belgium
M. Palkovic , IMEC vzw, Leuven, Belgium
pp. 205-212
Session 10: Energy and Performance Optimizations

Parameterized Looped Schedules for Compact Representationof Execution Sequences (Abstract)

Ming-Yung Ko , University of Maryland at College Park, USA
Sebastian Puthenpurayil , University of Maryland at College Park, USA
Claudiu Zissulescu , Leiden University, The Netherlands
pp. 223-230

An Improved Systolic Architecture for LU Decomposition (Abstract)

DaeGon Kim , Colorado State University
Sanjay V. Rajopadhye , Colorado State University
pp. 231-238

Dual-Processor Design of Energy Efficient Fault-Tolerant System (Abstract)

Pushkin R. Pari , Intel Technology India Pvt. Ltd. Bangalore, India
Gang Qu , University of Maryland
Shaoxiong Hua , Synopsys Inc., Mountain View, CA
pp. 239-244

An Energy-Delay Efficient Subword Permutation Unit (Abstract)

Dimitris Nikolos , University of Patras, 26500 Patras, Greece
Costas Galanopoulos , University of Patras, 26500 Patras, Greece
Christos Mavrokefalidis , University of Patras, 26500 Patras, Greece
Giorgos Dimitrakopoulos , University of Patras, 26500 Patras, Greece
pp. 245-252
Session 11: Video, Coding and Cryptography

Architecture design of an H.264/AVC decoder for real-time FPGA implementation (Abstract)

Marcin Lukowiak , Rochester Institute of Technology, Rochester, New York
Thomas Warsaw , Harris Corporation 1680 University Avenue Rochester, New York
pp. 253-256

Dynamic Voltage Scaling for Power Efficient MPEG4-SP Implementation (Abstract)

Antoni Portero , University Autonomous of Barcelona
Marius Monton , University Autonomous of Barcelona
Francky Cathoor , ESAT - INSYS, Kapeldreef 75, K.U.Leuven, BE-3001 Heverlee, Belgium
Borja Mart?nez , University Autonomous of Barcelona
Guillermo Talavera , University Autonomous of Barcelona
Jordi Carabina , University Autonomous of Barcelona
pp. 257-260

Dynamic-SIMD for lens distortion compensation (Abstract)

Twan Basten , Eindhoven University of Technology, The Netherlands
Bart Mesman , Eindhoven University of Technology, The Netherlands
Henk Corporaal , Eindhoven University of Technology, The Netherlands
Hamed Fatemi , Eindhoven University of Technology, The Netherlands
pp. 261-264

High Speed Channel Coding Architectures for the Uncoordinated OR Channel (Abstract)

M. Griot , UC Los Angeles, USA
R. Wesel , UC Los Angeles, USA
H. Chan , UC Los Angeles, USA
A. Vila Casado , UC Los Angeles, USA
I. Verbauwhede , ESAT/SCD-COSIC K.U.Leuven, Belgium
pp. 265-268

Efficient Group KeyManagement with Tamper-resistant ISA Extensions (Abstract)

Jun Yang , University of California at Riverside
Lan Gao , University of California at Riverside
Youtao Zhang , University of Pittsburgh
pp. 269-274

Speeding Up AES By Extending a 32 bit Processor Instruction Set (Abstract)

Francesco Regazzoni , ALaRI, University of Lugano, Switzerland
Luca Breveglieri , Politecnico di Milano, Italy
Farina Roberto , CEFRIEL - Politecnico di Milano, Italy
Guido Marco Bertoni , ST Microelectronics Agrate Briaznza, Italy
pp. 275-282
Session 12: Memory and Processor Synthesis

Buffer and register allocation for memory space optimization (Abstract)

F. Coelho , Ecole des mines de Paris, France
El. Aboulhamid , Universite de Montreal, Canada
G. Nicolescu , Ecole Polytechnique de Montreal, Canada
Y. Bouchebaba , Ecole Polytechnique de Montreal, Canada
pp. 283-290

New Schemes in Clustered VLIW Processors Applied to Turbo Decoding (Abstract)

Marisa Lopez-Vallejo , ETSI Telecomunicacion (UPM) Ciudad Universitaria, Madrid, Spain
Pablo Ituero , ETSI Telecomunicacion (UPM) Ciudad Universitaria, Madrid, Spain
pp. 291-296

Evaluating Hardware Support for Reference Counting Using Software Configurable Processors (Abstract)

Feng Xian , University of Nebraska-Lincoln
Witawas Srisa-an , University of Nebraska-Lincoln
Hong Jiang , University of Nebraska-Lincoln
pp. 297-302

Architectural Support on Object-Oriented Programming in a JAVA Processor (Abstract)

Tan Yiyu , City University of Hong Kong
Yau Chihang , City University of Hong Kong
Anthony Fong , City University of Hong Kong
pp. 303-310
Session 13: Matrix and Imaging Designs

Reconfigurable Fixed Point Dense and Sparse Matrix-Vector Multiply/Add Unit (Abstract)

Humberto Calderon , Electrical Engineering Dept.,EEMCS,TU Delft, The Netherlands
Stamatis Vassiliadis , Electrical Engineering Dept.,EEMCS,TU Delft, The Netherlands
pp. 311-316

High Performance VLSI Architecture Design for H.264 CAVLC Decoder (Abstract)

Mythri Alle , CAD Lab, Indian Institute of Science, Bangalore
J Biswas , CAD Lab, Indian Institute of Science, Bangalore
S. K. Nandy , CAD Lab, Indian Institute of Science, Bangalore
pp. 317-322

An FPGA-Based Application-Specific Processor for Efficient Reduction of Multiple Variable-Length Floating-Point Data Sets (Abstract)

Richard D. Anderson , U.S. Army Major Shared Resource Center Vicksburg, Mississippi
Gerald R. Morris , University of Southern California
Viktor K. Prasanna , University of Southern California
pp. 323-330

A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing (Abstract)

Benno Heigl , Siemens AG, Medical Solutions (AX), Forchheim, Germany.
Hritam Dutta , University of Erlangen-Nuremberg, Germany
Frank Hannig , University of Erlangen-Nuremberg, Germany
Heinz Hornegger , Siemens AG, Medical Solutions (AX), Forchheim, Germany.
Jurgen Teich , University of Erlangen-Nuremberg, Germany
pp. 331-340
Session 14: Cryptographic and Coding Applications

An Adaptable And Scalable Asymmetric Cryptographic Processor (Abstract)

Maire McLoone , Queen?s University of Belfast, Belfast, Northern Ireland
Neil Smyth , Queen?s University of Belfast, Belfast, Northern Ireland
John V. McCanny , Queen?s University of Belfast, Belfast, Northern Ireland
pp. 341-346

Low-Cost Elliptic Curve Digital Signature Coprocessor for Smart Cards (Abstract)

Renaud Ambroise , Universite Catholique de Louvain, Belgium
David Bol , Universite Catholique de Louvain, Belgium
Jean-Didier Legat , Universite Catholique de Louvain, Belgium
Guerric Meurice de Dormale , Universite Catholique de Louvain, Belgium
Jean-Jacques Quisquater , Universite Catholique de Louvain, Belgium
pp. 347-353

Throughput Optimized SHA-1 Architecture Using Unfolding Transformation (Abstract)

Yong Ki Lee , University of California, Los Angeles
Herwin Chan , University of California, Los Angeles
Ingrid Verbauwhede , Katholieke Universiteit Leuven
pp. 354-359

Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation (Abstract)

Predrag Radosavljevic , Rice University, Houston, TX
Joseph R. Cavallaro , Rice University, Houston, TX
Marjan Karkooti , Rice University, Houston, TX
pp. 360-367
Author Index

Author Index (PDF)

pp. 368
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