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IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06) (2006)
Steamboat Springs, Colorado, USA
Sept. 11, 2006 to Sept. 13, 2006
ISSN: 1063-6862
ISBN: 0-7695-2682-9
pp: 311-316
Humberto Calderon , Electrical Engineering Dept.,EEMCS,TU Delft, The Netherlands
Stamatis Vassiliadis , Electrical Engineering Dept.,EEMCS,TU Delft, The Netherlands
ABSTRACT
In this paper, we propose a reconfigurable hardware accelerator for fixed-point-matrix-vector-multiply/add operations, capable to work on dense and sparse matrices formats. The prototyped hardware unit accommodates 4 dense or sparse matrix inputs and performs computations in a space parallel design achieving 4 multiplications and up to 12 additions at 120 MHz over an xc2vp100-6 FPGA device, reaching a throughput of 1.9 GOPS. A total of 11 units can be integrated in the same FPGA chip, achieving a performance of 21 GOPS.
INDEX TERMS
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CITATION

H. Calderon and S. Vassiliadis, "Reconfigurable Fixed Point Dense and Sparse Matrix-Vector Multiply/Add Unit," IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06)(ASAP), Steamboat Springs, Colorado, USA, 2006, pp. 311-316.
doi:10.1109/ASAP.2006.58
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