IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06) (2006)
Steamboat Springs, Colorado, USA
Sept. 11, 2006 to Sept. 13, 2006
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASAP.2006.10
Giorgos Dimitrakopoulos , University of Patras, 26500 Patras, Greece
Christos Mavrokefalidis , University of Patras, 26500 Patras, Greece
Costas Galanopoulos , University of Patras, 26500 Patras, Greece
Dimitris Nikolos , University of Patras, 26500 Patras, Greece
Subword permutations are useful in many multimedia and cryptographic applications. Specialized instructions have been added to the instruction set of general-purpose processors to efficiently implement the required data rearrangements. In this paper, the design of a new energy-delay efficient subword permutation unit is examined. The proposed architecture has been derived by mapping the functionality of one of the most powerful permutation instructions (GRP) to a new enhanced linear sorting network. The introduced subword permutation unit is fast and achieves significant area and energy reductions compared to previous implementations. Also its regularity and its reduced wiring enables efficient VLSI implementations. The efficiency of the proposed architecture has been validated using static CMOS implementations in a standard performance 130nm CMOS technology.
D. Nikolos, C. Galanopoulos, C. Mavrokefalidis and G. Dimitrakopoulos, "An Energy-Delay Efficient Subword Permutation Unit," IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06)(ASAP), Steamboat Springs, Colorado, USA, 2006, pp. 245-252.