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2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors (2005)
Samos, Greece
July 23, 2005 to July 25, 2005
ISSN: 1063-6862
ISBN: 0-7695-2407-9
TABLE OF CONTENTS
Introduction

External referees (PDF)

pp. xiii
Session 1: Codesign Specification and Synthesis

External referees (PDF)

pp. xiii
Cover Pages
Introduction
Keynote
Session 1: Codesign Specification and Synthesis

Using Symbolic Feasibility Tests during Design Space Exploration of Heterogeneous Multi-Processor Systems (Abstract)

Frank Hannig , Department of Computer Science 12 University of Erlangen-Nuremberg, Germany
Christian Haubelt , Department of Computer Science 12 University of Erlangen-Nuremberg, Germany
J?urgen Teich , Department of Computer Science 12 University of Erlangen-Nuremberg, Germany
Thomas Schlichter , Department of Computer Science 12 University of Erlangen-Nuremberg, Germany
pp. 9-14

Artificial Deadlock Detection in Process Networks for ECLIPSE (Abstract)

Bharath. N , CAD Laboratory Supercomputer Education and Research Centre Indian Institute of Science Bangalore, India
Nagaraju Bussa , Philips Research India - Bangalore, Philips Innovation Campus Bangalore, India
pp. 22-27

Hardware/Software Interface for Multi-Dimensional Processor Arrays (Abstract)

Alain Darte , CNRS, LIP, ENS-Lyon 46, All?e d?Italie 69364 Lyon Cedex 07 France
Tanguy Risset , Inria, LIP, ENS-Lyon 46, All?e d?Italie 69364 Lyon Cedex 07 France
Steven Derrien , IFSIC, IRISA Campus de Beaulieu 35042 Rennes Cedex
pp. 28-35

Casablanca II: Implementation of a Real-Time RISC (Abstract)

Kiyofumi Tanaka , School of Information Science, Japan Advanced Institute of Science and Technology
pp. 36-42

Behavioral speci.cation of control interface for signal processing applications (Abstract)

Jerome Lemaitre , ASTRON, R&D Laboratory Oude Hoogeveensedijk 7991 PD Dwingeloo, The Netherlands
Ed Deprettere , LIACS, Leiden University NielsBohrweg 1 2333 CA Leiden, The Netherlands
Sylvain Alliot , ASTRON, R&D Laboratory Oude Hoogeveensedijk 7991 PD Dwingeloo, The Netherlands
pp. 43-49

Speedups from Partitioning Critical Software Parts to Coarse-Grain Reconfigurable Hardware (Abstract)

G. Dimitroulakos , VLSI Design Laboratory, ECE Department, University of Patras, Rio, 26500, Greece
M. D. Galanis , VLSI Design Laboratory, ECE Department, University of Patras, Rio, 26500, Greece
C. E. Goutis , VLSI Design Laboratory, ECE Department, University of Patras, Rio, 26500, Greece
pp. 50-59

A SW/Configware Codesign Methodology for Control Dominated Applications (Abstract)

K. Ben Chehida , I3S, University of Nice Sophia Antipolis, CNRS - France
M. Auguin , I3S, University of Nice Sophia Antipolis, CNRS - France
pp. 56-64
Session 2: (Special) System Level Soc Design

Towards a Framework for System-Level Design of Multiprocessor SoC Platforms for Media Processing (Abstract)

Samarjit Chakraborty , Department of Computer Science National University of Singapore
pp. 65-72

Communication-Centric SoC Design for Nanoscale Domain (Abstract)

Radu Marculescu , Department of Electrical and Computer Engineering Carnegie Mellon University
Umit Y. Ogras , Department of Electrical and Computer Engineering Carnegie Mellon University
Jingcao Hu , Department of Electrical and Computer Engineering Carnegie Mellon University
pp. 73-78

Using TLM for Exploring Bus-based SoC Communication Architectures (Abstract)

Sudeep Pasricha , Center for Embedded Computer Systems University of California, Irvine, CA
Mohamed Ben-Romdhane , Conexant Systems Inc.Newport Beach, CA
pp. 79-85

Exploring Design Space of VLIW Architectures (Abstract)

Vincenzo Catania , Dipartimento di Ingegneria Informatica e delle Telecomunicazioni Universit`a di Catania, Italy
Maurizio Palesi , Dipartimento di Ingegneria Informatica e delle Telecomunicazioni Universit`a di Catania, Italy
Davide Patti , Dipartimento di Ingegneria Informatica e delle Telecomunicazioni Universit`a di Catania, Italy
Giuseppe Ascia , Dipartimento di Ingegneria Informatica e delle Telecomunicazioni Universit`a di Catania, Italy
pp. 86-91

The Midlifekicker Microarchitecture Evaluation Metric (Abstract)

Georgi N. Gaydadjiev , Computer Engineering TU Delft the Netherlands
Leonel Sousa , Electrical and Computer Engineering IST/INESC-ID Lisboa, Portugal
Stamatis Vassiliadis , Computer Engineering TU Delft the Netherlands
pp. 92-100
Session 3: Applications

Design of a Hardware Accelerator for Density Based Clustering Applications (Abstract)

Jayaprakash Pisharath , Dept. of Electrical and Computer Engineering Northwestern University Evanston IL USA
Alok Choudhary , Dept. of Electrical and Computer Engineering Northwestern University Evanston IL USA
pp. 101-106

Complex Fixed-Point Matrix Inversion Using Transport Triggered Architecture (Abstract)

Adrian Burian , Nokia Research Center Visiokatu Tampere, Finland
Perttu Salmela , Institute of Digital and Computer Systems Tampere University of Technology, Tampere, Finland
Jarmo Takala , Institute of Digital and Computer Systems Tampere University of Technology, Tampere, Finland
pp. 107-112

A Parallel Automaton String Matching with Pre-Hashing and Root-Indexing Techniques for Content Filtering Coprocessor (Abstract)

Ying-Dar Lin , National Chiao Tung University, Taiwan
Kuo-Kun Tseng , National Chiao Tung University, Taiwan
Tsern-Huei Lee , National Chiao Tung University, Taiwan
Yuan-Cheng Lai , National Taiwan University of Science and Technology, Taiwan
pp. 113-118

Eliminating Sorting in IP Lookup Devices using Partitioned Table (Abstract)

Gyungho Lee , Electrical and Computer Engineering University of Illinois at Chicago
Enrico Ng , Electrical and Computer Engineering University of Illinois at Chicago
pp. 119-126
Session 4: Architectures, ISA & Microarchitecture

Multiply-Accumulate Architecture for a Special Class of Optimal Extension Fields (Abstract)

Earl E. Jr. Swartzlander , Department of Electrical & Computer Engineering The University of Texas at Austin
Moboluwaji O. Sanu , Department of Electrical & Computer Engineering The University of Texas at Austin
pp. 134-139

Automated Instruction-Set Extension of Embedded Processors with Application to MPEG-4 Video Encoding (Abstract)

Nikolaos Kavvadias , Section of Electronics and Computers, Department of Physics Aristotle University of Thessaloniki, 54124 Thessaloniki, Greece
Spiridon Nikolaidis , Section of Electronics and Computers, Department of Physics Aristotle University of Thessaloniki, 54124 Thessaloniki, Greece
pp. 140-145

Instruction Set Architecture Enhancements for Video Processing (Abstract)

Jan-Willem van de Waerdt , Philips Semiconductors, San Jose, CA, USA
Stamatis Vassiliadis , Delft University of Technology, Delft, The Netherlands
pp. 146-153

Instruction Set Customization of Application Speci.c Processors for Network Processing: A Case Study (Abstract)

Kingshuk Karuri , Institute for Integrated Signal Processing Systems RWTH Aachen University, Germany
Hanno Scharwaechter , Institute for Integrated Signal Processing Systems RWTH Aachen University, Germany
Gerd Ascheid , Institute for Integrated Signal Processing Systems RWTH Aachen University, Germany
Stefan Kraemer , Institute for Integrated Signal Processing Systems RWTH Aachen University, Germany
Anupam Chattopadhyay , Institute for Integrated Signal Processing Systems RWTH Aachen University, Germany
Rainer Leupers , Institute for Integrated Signal Processing Systems RWTH Aachen University, Germany
Mohammad Mostafizur Rahman Mozumdar , Institute for Integrated Signal Processing Systems RWTH Aachen University, Germany
Heinrich Meyr , Institute for Integrated Signal Processing Systems RWTH Aachen University, Germany
pp. 154-160

Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable Arrays (Abstract)

Michalis D. Galanis , VLSI Design Laboratory, ECE Department, University of Patras, Patras, Greece
Costas E. Goutis , VLSI Design Laboratory, ECE Department, University of Patras, Patras, Greece
Gregory Dimitroulakos , VLSI Design Laboratory, ECE Department, University of Patras, Patras, Greece
pp. 161-168

Architectural Support for Accelerating Congestion Control Applications in Network Processors (Abstract)

Eugene John , The University of Texas at San Antonio
Byeong Kil Lee , The University of Texas at Austin
Lizy Kurian John , The University of Texas at Austin
pp. 169-178
Session 5: Power Aware Systems & VLSI CAD

Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application (Abstract)

Andy Lambrechts , IMEC vzw, Belgium 2Dept of Electrical Engineering, K.U.L., Belgium
Fr?ed?eric Robert , MiEL, U.L.B., Belgium
Geert Deconinck , Dept of Electrical Engineering, K.U.L., Belgium
Tom Vander Aa , Dept of Electrical Engineering, K.U.L., Belgium
Jordi Carrabina , Dept of Computer Science, U.A.B., Spain
Diederik Verkest , Dept of Electrical Engineering, V.U.B., Belgium 4MiEL, U.L.B., Belgium
Francky Catthoor , Dept of Electrical Engineering, K.U.L., Belgium
Henk Corporaal , Dept of Electrical Engineering, TU/e, The Netherlands
Murali Jayapala , Dept of Electrical Engineering, K.U.L., Belgium
Guillermo Talavera , Dept of Computer Science, U.A.B., Spain 6Dept of Electrical Engineering, TU/e, The Netherlands
Praveen Raghavan , IMEC vzw, Belgium, Dept of Electrical Engineering, K.U.L., Belgium
Anthony Leroy , MiEL, U.L.B., Belgium
pp. 179-184

CASPER: An Integrated Energy-Driven Approach for Task Graph Scheduling on Distributed Embedded Systems (Abstract)

Shuvra S. Bhattacharyya , ECE Department and Institute for Advanced Computer Studies University of Maryland, College Park, MD
Gang Qu , ECE Department and Institute for Advanced Computer Studies University of Maryland, College Park, MD
Vida Kianzad , ECE Department and Institute for Advanced Computer Studies University of Maryland, College Park, MD
pp. 191-197

Via-Aware Global Routing for Good VLSI Manufacturability and High Yield (Abstract)

Guiying Yan , Inst Applied Math CAS Beijing, P. R. China
Xianlong Hong , Computer Science & Technology Dept. Tsinghua Univ. Beijing, P. R. China
Tong Jing , Computer Science & Technology Dept. Tsinghua Univ. Beijing, P. R. China
Xiaodong Hu , Inst Applied Math CAS Beijing, P. R. China
Yang Yang , Computer Science & Technology Dept. Tsinghua Univ. Beijing, P. R. China
Qi Zhu , EECS Dept. UC at Berkeley U. S. A.
Yu Hu , Computer Science & Technology Dept. Tsinghua Univ. Beijing, P. R. China
pp. 198-203
Session 6: (Special) Reconfigurable Computing

Zippy - A coarse-grained reconfigurable array with support for hardware virtualization (Abstract)

Christian Plessl , Computer Engineering and Networks Lab ETH Z?urich, Switzerland
Marco Platzner , Department of Computer Science University of Paderborn, Germany
pp. 213-218

An Image Processor for Digital Film (Abstract)

Amilcar do Carmo Lucas , Institute of Computer and Communication Network Engineering Technical University Braunschweig, Germany
Rolf Ernst , Institute of Computer and Communication Network Engineering Technical University Braunschweig, Germany
pp. 219-224

On Estimations for Compiling Software to FPGA-based Systems (Abstract)

Jo?o M. P. Cardoso , Campus de Gambelas, 8000 - 117 Faro, Portugal
pp. 225-230

A Programmable DSP Architecture for Wireless Communication Systems (Abstract)

Nozar Tabrizi , Kettering University Flint, Michigan
Nader Bagherzadeh , EECS Department,UC Irvine
Amir Kamalizad , EECS Department, UC Irvine
Akira Hatanaka , EECS Department,UC Irvine
pp. 231-238

Customising Application-Speci.c Multiprocessor Systems: a Case Study (Abstract)

Andreas Fidjeland , Imperial College London 180 Queen?s Gate London
Wayne Luk , Imperial College London 180 Queen?s Gate London
pp. 239-246
Session 7: (Special) Nanocomputing

Faults, Error Bounds and Reliability of Nanoelectronic Circuits (Abstract)

Jie Han , Department of Electrical and Computer Engineering,University of Florida, Gainesville, FL, USA
Erin Taylor , Department of Electrical and Computer Engineering,University of Florida, Gainesville, FL, USA
Jos? Fortes , Department of Electrical and Computer Engineering,University of Florida, Gainesville, FL, USA
Jianbo Gao , Department of Electrical and Computer Engineering,University of Florida, Gainesville, FL, USA
pp. 247-253

Logic Models Supporting the Design of MOBILE-based RTD Circuits (Abstract)

Mar?a J. Avedillo , Instituto de Microelectr?nica de Sevilla IMSE-CNM
Jos? M. Quintana , Instituto de Microelectr?nica de Sevilla IMSE-CNM
Hector Pettenghi , Instituto de Microelectr?nica de Sevilla IMSE-CNM
pp. 254-259

CONAN - A Design Exploration Framework for Reliable Nano-Electronics (Abstract)

O. Soffke , Darmstadt University of Technology, Darmstadt, Germany.
M. Glesner , Darmstadt University of Technology, Darmstadt, Germany.
A. Rubio , Polytechnic University of Catalonia, Barcelona, Spain.
Y. Leblebici , Swiss Federal Institute of Technology, Lausanne, Switzerland.
P. Zipf , Darmstadt University of Technology, Darmstadt, Germany.
S. Cotofana , Delft University of Technology, Delft, The Netherlands.
A. Ionescu , Swiss Federal Institute of Technology, Lausanne, Switzerland.
A. Schmid , Swiss Federal Institute of Technology, Lausanne, Switzerland.
pp. 260-267

Analytical approach to massively parallel architectures for nanotechnologies (Abstract)

Bjorn Jager , Heinz Nixdorf Institute, System and Circuit Technology University of Paderborn, Germany
Jorg Christian Niemann , Heinz Nixdorf Institute, System and Circuit Technology University of Paderborn, Germany
Ulrich Ruckert , Heinz Nixdorf Institute, System and Circuit Technology University of Paderborn, Germany
pp. 268-275

On the Advantages of Serial Architectures for Low-Power Reliable Computations (Abstract)

J. Nyathi , School of EECS, Washington State University, Pullman, Washington, USA
A. Djupdal , Department of CS&IT, Norwegian University of Science and Technology, Norway
V. Beiu , School of EECS, Washington State University, Pullman, Washington, USA
S. Aunet , Department of Informatics, University of Oslo, Norway
R. R. III Rydberg , School of EECS, Washington State University, Pullman, Washington, USA
pp. 276-281

Reducing Interconnection Resource Overhead in Nano-scale FPGAs through MVL Signal Systems (Abstract)

LP Maguire , Intelligent Systems Engineering Laboratory, Faculty of Engineering, University of Ulster Magee Campus, Derry, Northern Ireland
TM McGinnity , Intelligent Systems Engineering Laboratory, Faculty of Engineering, University of Ulster Magee Campus, Derry, Northern Ireland
PM Kelly , Intelligent Systems Engineering Laboratory, Faculty of Engineering, University of Ulster Magee Campus, Derry, Northern Ireland
pp. 282-287

Simple 4-Bit Processor Based On Quantum-Dot Cellular Automata (QCA) (Abstract)

Mazur, G. Schulhof , ATIPS Laboratory, University of Calgary, Calgary, Canada
K. Walus , ATIPS Laboratory, University of Calgary, Calgary, Canada
G. A. Jullien , ATIPS Laboratory, University of Calgary, Calgary, Canada
pp. 288-293

High Radix Addition Via Conditional Charge Transport in Single Electron Tunneling Technology (Abstract)

Casper Lageweg , Computer Engineering Lab Delft University of Technology Delft, The Netherlands
Sorin Cotofana , Computer Engineering Lab Delft University of Technology Delft, The Netherlands
Cor Meenderinck , Computer Engineering Lab Delft University of Technology Delft, The Netherlands
pp. 294-302
Session 8: Arithmetic

Decimal Floating-Point Square Root Using Newton-Raphson Iteration (Abstract)

Liang-Kai Wang , Dept. of ECE, University of Wisconsin-Madison, Madison, WI
Michael J. Schulte , Dept. of ECE, University of Wisconsin-Madison, Madison, WI
pp. 309-315

Variable Radix Real and Complex Digit-Recurrence Division (Abstract)

Jean-Michel Muller , CNRS-Laboratoire CNRS-ENSL-INRIA-UCBL LIP Ecole Normale Sup?erieure de Lyon 46 All?ee d?Italie, 69364 Lyon Cedex 07, FRANCE
Milos D. Ercegovac , Computer Science Department, 4732 Boelter Hall University of California at Los Angeles Los Angeles, CA 90095, USA
pp. 316-321

On-line Multioperand Addition Based on On-line Full Adders (Abstract)

Jose M. Prades , Dept. of Computer Architecture University of Malaga. SPAIN
Julio Villalba , Dept. of Computer Architecture University of Malaga. SPAIN
Emilio L. Zapata , Dept. of Computer Architecture University of Malaga. SPAIN
Javier Hormigo , Dept. of Computer Architecture University of Malaga. SPAIN
pp. 322-327

Table-based polynomials for fast hardware function evaluation (Abstract)

Jeremie Detrey , LIP,? Ecole Normale Sup?erieure de Lyon France
Florent de Dinechin , LIP,? Ecole Normale Sup?erieure de Lyon France
pp. 328-333

Small FPGA polynomial approximations with 3-bit coefficients and low-precision estimations of the powers of x (Abstract)

Nicolas Veyrat-Charvillon , Arenaire project (CNRS-ENS Lyon-INRIA-UCBL), LIP Ecole Normale Sup?erieure de Lyon (ENS Lyon) Lyon, France
Romain Michard , Arenaire project (CNRS-ENS Lyon-INRIA-UCBL), LIP Ecole Normale Sup?erieure de Lyon (ENS Lyon) Lyon, France
Arnaud Tisserand , Arenaire project (CNRS-ENS Lyon-INRIA-UCBL), LIP Ecole Normale Sup?erieure de Lyon (ENS Lyon) Lyon, France
pp. 334-342
Session 9: Cryptography and Coding

Architectural Extensions for Elliptic Curve Cryptography over GF(2^m ) on 8-bit Microprocessors (Abstract)

Sheueling Chang-Shantz , Sun Microsystems Laboratories Menlo Park, California, USA
Nils Gura , Sun Microsystems Laboratories Menlo Park, California, USA
Arvinderpal Wander , Sun Microsystems Laboratories Menlo Park, California, USA
Vipul Gupta , Sun Microsystems Laboratories Menlo Park, California, USA
Hans Eberle , Sun Microsystems Laboratories Menlo Park, California, USA
pp. 343-349

Side-channel aware design: Algorithms and Architectures for Elliptic Curve Cryptography over GF(2^n ) (Abstract)

Nele Mentens , Katholieke Universiteit Leuven, ESAT/SCD-COSIC
Ingrid Verbauwhede , University of California, El. Engineering Dept. Los Angeles, CA 90095
Bart Preneel , Katholieke Universiteit Leuven, ESAT/SCD-COSIC
Lejla Batina , Katholieke Universiteit Leuven, ESAT/SCD-COSIC
pp. 350-355

On-Chip Lookup Tables for Fast Symmetric-Key Encryption (Abstract)

A. Murat Fiskiran , Princeton Architecture Laboratory for Multimedia and Security (PALMS) Department of Electrical Engineering, Princeton University
Ruby B. Lee , Princeton Architecture Laboratory for Multimedia and Security (PALMS) Department of Electrical Engineering, Princeton University
pp. 356-363

Instruction Set Extensions for Reed-Solomon Encoding and Decoding (Abstract)

Michael J. Schulte , Dept. of ECE University of Wisconsin-Madison, Madison
John Glossner , Sandbridge Technologies White Plains, NY
Andrei Iancu , Sandbridge Technologies White Plains, NY
Daniel Iancu , Sandbridge Technologies White Plains, NY
Suman Mamidi , Dept. of ECE University of Wisconsin-Madison, Madison
pp. 364-369

256-State Rate 1/2 Viterbi Decoder on TTA Processor (Abstract)

Perttu Salmela , Institute of Digital and Computer Systems Tampere University of Technology,Tampere, Finland
Teemu Sipila , Institute of Digital and Computer Systems Tampere University of Technology,Tampere, Finland
Tuomas Jarvinen , Institute of Digital and Computer Systems Tampere University of Technology,Tampere, Finland
Jarmo Takala , Nokia Mobile Phones, Oulu, Finland
pp. 370-378
Session 10: Signal and Video Processing

Recursive Filtering on a Vector DSP with Linear Speedup (Abstract)

M. Van Der Horst , Technische Universiteit Eindhoven, P.O. Box 5 13,5600 MB Eindhoven, Netherlands
K. Van Berkel , Technische Universiteit Eindhoven, P.O. Box 5 13,5600 MB Eindhoven, Netherlands
R. Mak , Technische Universiteit Eindhoven, P.O. Box 5 13,5600 MB Eindhoven, Netherlands
J Lukkien , Technische Universiteit Eindhoven, P.O. Box 5 13,5600 MB Eindhoven, Netherlands
pp. 379-386

A Fault-Tolerant Modulus Replication Complex FIR Filter (Abstract)

Steiner, P. Chan , Advanced Technology Information Processing Systems Laboratory, University of Calgary Alberta, CANADA
L. Imbert , Centre National de la Recherche Scienti?que, France and ATIPS Laboratory, Centre for Information Security and Cryptography, University of Calgary
V.S. Dimitrov , Advanced Technology Information Processing Systems Laboratory, University of Calgary Alberta, CANADA
G.A. Jullien , Advanced Technology Information Processing Systems Laboratory, University of Calgary Alberta, CANADA
G.H. McGibney , TRLabs
pp. 387-392

Performance Comparison of SIMD Implementations of the Discrete Wavelet Transform (Abstract)

Asadollah Shahbahrami , Computer Engineering Laboratory Faculty of Electrical Engineering, Mathematics, and Computer Science Delft University of Technology, The Netherlands
Stamatis Vassiliadis , Computer Engineering Laboratory Faculty of Electrical Engineering, Mathematics, and Computer Science Delft University of Technology, The Netherlands
Ben Juurlink , Computer Engineering Laboratory Faculty of Electrical Engineering, Mathematics, and Computer Science Delft University of Technology, The Netherlands
pp. 393-398

Real-time H/W Implementation of the Approximate Discrete Radon Transform (Abstract)

A. K. Somani , Dependable Computing and Networking Laboratory Department of Electrical & Computer Engineering Iowa State University, Ames, IA, 50011, USA
N. A. VanderHorn, , Dependable Computing and Networking Laboratory Department of Electrical & Computer Engineering Iowa State University, Ames, IA, 50011, USA
M. T. Frederick , Dependable Computing and Networking Laboratory Department of Electrical & Computer Engineering Iowa State University, Ames, IA, 50011, USA
pp. 399-404

A Thread and Data-Parallel MPEG-4 Video Encoder for a System-On-Chip Multiprocessor (Abstract)

Tom R. Jacobs , Department of Electronic and Electrical Engineering University of Loughborough, Loughborough, UK
Jose L. Nunez-Yanez , Department of Electronic Engineering University of Bristol, Bristol, UK
pp. 405-410

Design and Implementation of a High-Performance and Silicon Efficient Arithmetic Coding Accelerator for the H.264 Advanced Video Codec (Abstract)

Jos? L. N??ez-Y??ez, , Department of Electronic Engineering, University of Bristol, UK
Vassilios A. Chouliaras , Department of Electronic Engineering, University of Loughborough, UK
pp. 411-416
Author Index

Author Index (PDF)

pp. 417
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