2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) (2005)

Samos, Greece

July 23, 2005 to July 25, 2005

ISSN: 1063-6862

ISBN: 0-7695-2407-9

pp: 393-398

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASAP.2005.51

Asadollah Shahbahrami , Computer Engineering Laboratory Faculty of Electrical Engineering, Mathematics, and Computer Science Delft University of Technology, The Netherlands

Ben Juurlink , Computer Engineering Laboratory Faculty of Electrical Engineering, Mathematics, and Computer Science Delft University of Technology, The Netherlands

Stamatis Vassiliadis , Computer Engineering Laboratory Faculty of Electrical Engineering, Mathematics, and Computer Science Delft University of Technology, The Netherlands

ABSTRACT

<p>This paper focuses on SIMD implementations of the 2D discrete wavelet transform (DWT). The transforms considered are Daubechies? real-to-real method of four coef ficients (Daub-4) and the integer-to-integer (5, 3) lifting scheme. Daub-4 is implemented using SSE and the lifting scheme using MMX, and their performance is compared to C implementations on a Pentium 4 processor. The MMX implementation of the lifting scheme is up to 4.0x faster than the corresponding C program for a 1-level 2D DWT, while the SSE implementation of Daub-4 is up to 2.6x faster than the C version. It is shown that for some image sizes, the performance is significantly hampered by the so-called 64K aliasing problem, which occurs in the Pentium 4 when two data blocks are accessed that are a multiple of 64K apart. It is also shown that for the (5, 3) lifting scheme, a 12-bit word size is sufficient for a 5-level decomposition of the 2D DWT for images of up to 10 bits per pixel.</p>

INDEX TERMS

Discrete Wavelet Transform, lifting scheme, SIMD extensions.

CITATION

A. Shahbahrami, S. Vassiliadis and B. Juurlink, "Performance Comparison of SIMD Implementations of the Discrete Wavelet Transform,"

*2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)(ASAP)*, Samos, Greece, 2005, pp. 393-398.

doi:10.1109/ASAP.2005.51

CITATIONS