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2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) (2005)
Samos, Greece
July 23, 2005 to July 25, 2005
ISSN: 1063-6862
ISBN: 0-7695-2407-9
pp: 282-287
PM Kelly , Intelligent Systems Engineering Laboratory, Faculty of Engineering, University of Ulster Magee Campus, Derry, Northern Ireland
TM McGinnity , Intelligent Systems Engineering Laboratory, Faculty of Engineering, University of Ulster Magee Campus, Derry, Northern Ireland
LP Maguire , Intelligent Systems Engineering Laboratory, Faculty of Engineering, University of Ulster Magee Campus, Derry, Northern Ireland
ABSTRACT
<p>In nano-architectures, transistor counts will place extreme demands on interconnection resources. The chronic problem of interconnect area versus device area will become more acute than it currently is. Even with multi-layering of conductors there may still be attenuation and propagation delay issues which at the extremes of nano-architecture will severely limit performance. When re-configurable devices such as Field Programmable Gate Arrays (FPGAs) are considered the issue of interconnection resources becomes even more acute due to the inherent redundancy already apparent in existing devices. The authors propose the use of a Multiple Valued Signal System to increase functional density whilst reducing the interconnection resource overhead in FPGA based nano-architectures.</p>
INDEX TERMS
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CITATION

L. Maguire, T. McGinnity and P. Kelly, "Reducing Interconnection Resource Overhead in Nano-scale FPGAs through MVL Signal Systems," 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)(ASAP), Samos, Greece, 2005, pp. 282-287.
doi:10.1109/ASAP.2005.56
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