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2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) (2005)
Samos, Greece
July 23, 2005 to July 25, 2005
ISSN: 1063-6862
ISBN: 0-7695-2407-9
pp: 179-184
Andy Lambrechts , IMEC vzw, Belgium 2Dept of Electrical Engineering, K.U.L., Belgium
Praveen Raghavan , IMEC vzw, Belgium, Dept of Electrical Engineering, K.U.L., Belgium
Anthony Leroy , MiEL, U.L.B., Belgium
Guillermo Talavera , Dept of Computer Science, U.A.B., Spain 6Dept of Electrical Engineering, TU/e, The Netherlands
Tom Vander Aa , Dept of Electrical Engineering, K.U.L., Belgium
Murali Jayapala , Dept of Electrical Engineering, K.U.L., Belgium
Francky Catthoor , Dept of Electrical Engineering, K.U.L., Belgium
Diederik Verkest , Dept of Electrical Engineering, V.U.B., Belgium 4MiEL, U.L.B., Belgium
Geert Deconinck , Dept of Electrical Engineering, K.U.L., Belgium
Henk Corporaal , Dept of Electrical Engineering, TU/e, The Netherlands
Fr?ed?eric Robert , MiEL, U.L.B., Belgium
Jordi Carrabina , Dept of Computer Science, U.A.B., Spain
ABSTRACT
<p>Users expect future handheld devices to provide extended multimedia functionality and have long battery life. This type of application imposes heavy constraints on performance and power consumption and forces designers to optimize all parts of their platform. Evaluating the overall platform power breakdown is therefore critical to determine where to spend the efforts on power optimization. Surprisingly, few studies exist on that topic and decisions generally rely on common belief. We have realized a complete power breakdown for a realistic platform to identify the major power bottlenecks. This paper presents this power assessment of a realistic heterogeneous network on chip platform including processors, network and data/instruction memory hierarchy, running a video processing chain from camera to display. Our power breakdown identifies the main bottlenecks in the memory hierarchy and the foreground memory, and shows that global interconnect is not that critical for a well-optimized application mapping.</p>
INDEX TERMS
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CITATION

A. Lambrechts et al., "Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application," 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)(ASAP), Samos, Greece, 2005, pp. 179-184.
doi:10.1109/ASAP.2005.52
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