2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) (2005)
July 23, 2005 to July 25, 2005
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASAP.2005.40
Jan-Willem van de Waerdt , Philips Semiconductors, San Jose, CA, USA
Stamatis Vassiliadis , Delft University of Technology, Delft, The Netherlands
<p>This paper presents some of the enhancements to the TriMedia instruction set architecture (ISA), as supported by the TM3270 media-processor. We show how the new operations are used to optimize the individual MPEG2 encoder kernels. Furthermore, we quantify the contribution of these kernels to overall MPEG2 encoder performance. We introduce two-slot operations, collapsed load operations wit interpolations, and new multiplication operations. The encoder?s texture pipeline for a bi-directionally predicted 8x8 block is performed in 358 VLIW instructions. MPEG2 encoding at CIF resolution at 25 frames per second is achieved within 33.5 MHz. of processor performance.</p>
J. van de Waerdt and S. Vassiliadis, "Instruction Set Architecture Enhancements for Video Processing," 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)(ASAP), Samos, Greece, 2005, pp. 146-153.