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Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004. (2004)
Galveston, Texas
Sept. 27, 2004 to Sept. 29, 2004
ISSN: 1063-6862
ISBN: 0-7695-2226-2
TABLE OF CONTENTS

Defect-tolerant molecular electronics (PDF)

P.J. Kuekes , Hewlett-Packard Laboratories
pp. 2-3

Modeling and scheduling parallel data flow systems using structured systems of recurrence equations (PDF)

F. Charot , Irisa, Rennes, France
M. Nyamsi , Irisa, Rennes, France
P. Quinton , Irisa, Rennes, France
C. Wagner , Irisa, Rennes, France
pp. 6-16

Resource constrained and speculative scheduling of an algorithm class with run-time dependent conditionals (PDF)

F. Hannig , Dept. of Comput. Sci., Erlangen Univ., Nuremberg, Germany
J. Teich , Dept. of Comput. Sci., Erlangen Univ., Nuremberg, Germany
pp. 17-27

CHARMED: a multi-objective co-synthesis framework for multi-mode embedded systems (PDF)

V. Kianzad , Dept. of ECE, Maryland Univ., College Park, MD, USA
S.S. Bhattacharyya , Dept. of ECE, Maryland Univ., College Park, MD, USA
pp. 28-40

Reliability-aware co-synthesis for embedded systems (PDF)

Y. Xie , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., Philadelphia, PA, USA
L. Li , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., Philadelphia, PA, USA
M. Kandemir , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., Philadelphia, PA, USA
N. Vijaykrishnan , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., Philadelphia, PA, USA
M.J. Irwin , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., Philadelphia, PA, USA
pp. 41-50

Complex square root with operand prescaling (PDF)

M.D. Ercegovac , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 52-62

Parallel Montgomery multipliers (PDF)

M.O. Sanu , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
E.E. Swartzlander , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
C.M. Chase , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 63-72

Improved-throughput networks of basic on-line arithmetic modules for DSP applications (PDF)

A.F. Tenca , Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR, USA
A.C. Shantilal , Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR, USA
M.H. Sinky , Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR, USA
pp. 73-83

Decimal floating-point division using Newton-Raphson iteration (PDF)

Liang-Kai Wang , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
M.J. Schulte , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
pp. 84-95

A public-key cryptographic processor for RSA and ECC (PDF)

H. Eberle , Sun Microsystems Labs., Santa Clara, CA, USA
N. Gura , Sun Microsystems Labs., Santa Clara, CA, USA
S.C. Shantz , Sun Microsystems Labs., Santa Clara, CA, USA
V. Gupta , Sun Microsystems Labs., Santa Clara, CA, USA
L. Rarick , Sun Microsystems Labs., Santa Clara, CA, USA
pp. 98-110

Evaluating instruction set extensions for fast arithmetic on binary finite fields (PDF)

A.M. Fiskiran , Dept. of Electr. Eng., Princeton Univ., NJ, USA
R.B. Lee , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 125-136

Efficient processing of color image sequences using a color-aware instruction set on mobile systems (PDF)

Jongmyon Kim , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
D.S. Wills , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 137-149

Binary multiplication based on single electron tunneling (PDF)

C. Lageweg , Dept. of Microelectron. & Comput. Eng., Delft Univ. of Technol., Netherlands
S. Cotofana , Dept. of Microelectron. & Comput. Eng., Delft Univ. of Technol., Netherlands
S. Vassiliadis , Dept. of Microelectron. & Comput. Eng., Delft Univ. of Technol., Netherlands
pp. 152-166

A novel highly reliable low-power nano architecture when von Neumann augments Kolmogorov (PDF)

V. Beiu , Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA
pp. 167-177

Register organization for enhanced on-chip parallelism (PDF)

R. Sangireddy , Dept. of Electr. Eng., Texas Univ., Richardson, TX, USA
pp. 180-190

Design and evaluation of a network-based architecture for cryptographic devices (PDF)

L. Dilparic , Sch. of Informatics, Edinburgh Univ., UK
D.K. Arvind , Sch. of Informatics, Edinburgh Univ., UK
pp. 191-201

Switching-activity minimization on instruction-level loop for VLIW DSP applications (PDF)

Zili Shao , Dept. of Comput. Sci., Texas Univ., Richardson, TX, USA
Qingfeng Zhuge , Dept. of Comput. Sci., Texas Univ., Richardson, TX, USA
Meilin Liu , Dept. of Comput. Sci., Texas Univ., Richardson, TX, USA
Bin Xiao , Dept. of Comput. Sci., Texas Univ., Richardson, TX, USA
E.H.-M. Sha , Dept. of Comput. Sci., Texas Univ., Richardson, TX, USA
pp. 224-234

A digit-serial algorithm for the discrete logarithm modulo 2/sup k/ (PDF)

A. Fit-Florea , Southern Methodist Univ., Dallas, TX, USA
D.W. Matula , Southern Methodist Univ., Dallas, TX, USA
pp. 236-246

An algorithm and hardware architecture for integrated modular division and multiplication in GF(p) and GF(2/sup n/) (PDF)

L.A. Tawalbeh , Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR, USA
A.F. Tenca , Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR, USA
pp. 247-257

Detecting faults in four symmetric key block ciphers (PDF)

L. Breveglieri , Dept. of Electron. & Inf. Technol., Politecnico di Milano, Italy
pp. 258-268

A low-power carry skip adder with fast saturation (PDF)

M.J. Schulte , Sandbridge Technol., Inc., White Plains, NY, USA
K. Chirca , Sandbridge Technol., Inc., White Plains, NY, USA
J. Glossner , Sandbridge Technol., Inc., White Plains, NY, USA
H. Wang , Sandbridge Technol., Inc., White Plains, NY, USA
S. Mamidi , Sandbridge Technol., Inc., White Plains, NY, USA
P. Balzola , Sandbridge Technol., Inc., White Plains, NY, USA
pp. 269-279

A hierarchical classification scheme to derive interprocess communication in process networks (PDF)

A. Turjan , Leiden Inst. of Adv. Comput. Sci., Netherlands
B. Kienhuis , Leiden Inst. of Adv. Comput. Sci., Netherlands
E. Deprettere , Leiden Inst. of Adv. Comput. Sci., Netherlands
pp. 282-292

Efficient on-chip communications for data-flow IPs (PDF)

A. Fraboulet , Citi, Insa-Lyon, Villeurbanne, France
pp. 293-303

Automatic synthesis of customized local memories for multicluster application accelerators (PDF)

M. Kudlur , Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA
K. Fan , Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA
M. Chu , Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA
S. Mahlke , Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA
pp. 304-314

Optimized data-reuse in processor arrays (PDF)

S. Siegel , Dept. of Electr. Eng. & Inf. Technol., Dresden Univ. of Technol., Germany
R. Merker , Dept. of Electr. Eng. & Inf. Technol., Dresden Univ. of Technol., Germany
pp. 315-325

Hyper-programmable architectures for adaptable networked systems (PDF)

G. Brebner , Xilinx Res. Labs., San Jose, CA, USA
P. James-Roxby , Xilinx Res. Labs., San Jose, CA, USA
E. Keller , Xilinx Res. Labs., San Jose, CA, USA
C. Kulkarni , Xilinx Res. Labs., San Jose, CA, USA
pp. 328-338

Programming transparency and portable hardware interfacing: towards general-purpose reconfigurable computing (PDF)

M. Vuletic , Processor Archit. Lab., Swiss Fed. Inst. of Technol., Lausanne, Switzerland
L. Pozzi , Processor Archit. Lab., Swiss Fed. Inst. of Technol., Lausanne, Switzerland
P. Ienne , Processor Archit. Lab., Swiss Fed. Inst. of Technol., Lausanne, Switzerland
pp. 339-351

Families of FPGA-based algorithms for approximate string matching (PDF)

T. Van Court , Dept. of Electr. & Comput. Eng., Boston Univ., MA, USA
M.C. Herbordt , Dept. of Electr. & Comput. Eng., Boston Univ., MA, USA
pp. 354-364

Biosequence similarity search on the Mercury system (PDF)

P. Krishnamurthy , Dept. of Comput. Sci. & Eng., Washington Univ., St. Louis, WA, USA
J. Buhler , Dept. of Comput. Sci. & Eng., Washington Univ., St. Louis, WA, USA
R. Chamberlain , Dept. of Comput. Sci. & Eng., Washington Univ., St. Louis, WA, USA
M. Franklin , Dept. of Comput. Sci. & Eng., Washington Univ., St. Louis, WA, USA
M. Gyang , Dept. of Comput. Sci. & Eng., Washington Univ., St. Louis, WA, USA
J. Lancaster , Dept. of Comput. Sci. & Eng., Washington Univ., St. Louis, WA, USA
pp. 365-375

Stride permutation networks for array processors (PDF)

T. Jarvinen , Digital & Comput. Syst. Lab., Tampere Univ. of Technol., Finland
P. Salmela , Digital & Comput. Syst. Lab., Tampere Univ. of Technol., Finland
H. Sorokin , Digital & Comput. Syst. Lab., Tampere Univ. of Technol., Finland
J. Takala , Digital & Comput. Syst. Lab., Tampere Univ. of Technol., Finland
pp. 376-386

A packet scheduling algorithm for IPSec multi-accelerator based systems (PDF)

F. Castanier , Adv. Syst. Technol., ST Microelectron., Geneva, Switzerland
pp. 387-397

Design of the QBIC wearable computing platform (PDF)

O. Amft , Wearable Comput. Lab., ETH Zurich, Switzerland
M. Lauffer , Wearable Comput. Lab., ETH Zurich, Switzerland
S. Ossevoort , Wearable Comput. Lab., ETH Zurich, Switzerland
F. Macaluso , Wearable Comput. Lab., ETH Zurich, Switzerland
P. Lukowicz , Wearable Comput. Lab., ETH Zurich, Switzerland
G. Troster , Wearable Comput. Lab., ETH Zurich, Switzerland
pp. 398-410
Session 6: Arithmetic II

A Low-Power Carry Skip Adder with Fast Saturation (Abstract)

Michael J. Schulte , Sandbridge Technologies, Inc., White Plains, NY; University of Wisconsin, Madison, WI
Kai Chirca , Sandbridge Technologies, Inc., White Plains, NY
John Glossner , Sandbridge Technologies, Inc., White Plains, NY
Haoran Wang , Sandbridge Technologies, Inc., White Plains, NY
Suman Mamidi , Sandbridge Technologies, Inc., White Plains, NY; University of Wisconsin, Madison, WI
Pablo Balzola , Sandbridge Technologies, Inc., White Plains, NY
Stamatis Vassiliadis , Delft University of Technology, The Netherlands
pp. 269-279
Session 7: Communication, Interfaces and Memory

A Hierarchical Classification Scheme to Derive Interprocess Communication in Process Networks (Abstract)

Alexandru Turjan , Leiden Institute of Advanced Computer Science (LIACS), The Netherlands
Bart Kienhuis , Leiden Institute of Advanced Computer Science (LIACS), The Netherlands
Ed Deprettere , Leiden Institute of Advanced Computer Science (LIACS), The Netherlands
pp. 282-292

Efficient On-Chip Communications for Data-Flow IPs (Abstract)

Antoine Fraboulet , Citi, Insa-Lyon, France
Tanguy Risset , Inria, Lip, ENS-Lyon, France
pp. 293-303

Automatic Synthesis of Customized Local Memories for Multicluster Application Accelerators (Abstract)

Manjunath Kudlur , University of Michigan, Ann Arbor
Kevin Fan , University of Michigan, Ann Arbor
Michael Chu , University of Michigan, Ann Arbor
Scott Mahlke , University of Michigan, Ann Arbor
pp. 304-314

Optimized Data-Reuse in Processor Arrays (Abstract)

Sebastian Siegel , Dresden University of Technology, Germany
Renate Merker , Dresden University of Technology, Germany
pp. 315-325
Session 8: (Special) Reconfigurable Computing

Hyper-Programmable Architectures for Adaptable Networked Systems (Abstract)

Gordon Brebner , Xilinx Research Laboratories
Phil James-Roxby , Xilinx Research Laboratories
Eric Keller , Xilinx Research Laboratories
Chidamber Kulkarni , Xilinx Research Laboratories
pp. 328-338

Programming Transparency and Portable Hardware Interfacing: Towards General-Purpose Reconfigurable Computing (Abstract)

Miljan Vuletic , Swiss Federal Institute of Technology Lausanne, Switzerland
Laura Pozzi , Swiss Federal Institute of Technology Lausanne, Switzerland
Paolo Ienne , Swiss Federal Institute of Technology Lausanne, Switzerland
pp. 339-351
Session 9: Applications

Biosequence Similarity Search on the Mercury System (Abstract)

Praveen Krishnamurthy , Washington University in St. Louis
Jeremy Buhler , Washington University in St. Louis
Roger Chamberlain , Washington University in St. Louis
Mark Franklin , Washington University in St. Louis
Kwame Gyang , Washington University in St. Louis
Joseph Lancaster , Washington University in St. Louis
pp. 365-375

Stride Permutation Networks for Array Processors (Abstract)

Tuomas J?rvinen , Tampere University of Technology, Finland
Perttu Salmela , Tampere University of Technology, Finland
Harri Sorokin , Tampere University of Technology, Finland
Jarmo Takala , Tampere University of Technology, Finland
pp. 376-386

A Packet Scheduling Algorithm for IPSec Multi-Accelerator Based Systems (Abstract)

Fabien Castanier , ST Microelectronics
Alberto Ferrante , University of Milan
Vincenzo Piuri , University of Milan
pp. 387-397

Design of the QBIC Wearable Computing Platform (Abstract)

Oliver Amft , ETH Z?rich, Switzerland
Michael Lauffer , ETH Z?rich, Switzerland
Stijn Ossevoort , ETH Z?rich, Switzerland
Fabrizio Macaluso , ETH Z?rich, Switzerland
Paul Lukowicz , ETH Z?rich, Switzerland
Gerhard Tr?ster , ETH Z?rich, Switzerland
pp. 398-410

Author Index (PDF)

pp. 411-412
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