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2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors (2004)
Galveston, Texas
Sept. 27, 2004 to Sept. 29, 2004
ISSN: 1063-6862
ISBN: 0-7695-2226-2
TABLE OF CONTENTS
Keynote

Defect-Tolerant Molecular Electronics (PDF)

Philip J. Kuekes , Hewlett-Packard Laboratories
pp. 2-3
Session 1: Scheduling and Codesign

Modeling and Scheduling Parallel Data Flow Systems using Structured Systems of Recurrence Equations (Abstract)

Charles Wagner , Irisa, Campus de Beaulieu, France
Fran?ois Charot , Irisa, Campus de Beaulieu, France
Patrice Quinton , Irisa, Campus de Beaulieu, France
Madeleine Nyamsi , Irisa, Campus de Beaulieu, France
pp. 6-16

Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals (Abstract)

J? Teich , University of Erlangen-Nuremberg, Germany
Frank Hannig , University of Erlangen-Nuremberg, Germany
pp. 17-27

CHARMED: A Multi-Objective Co-Synthesis Framework for Multi-Mode Embedded Systems (Abstract)

Vida Kianzad , University of Maryland, College Park
Shuvra S. Bhattacharyya , University of Maryland, College Park
pp. 28-40

Reliability-Aware Co-Synthesis for Embedded Systems (Abstract)

L. Li , Pennsylvania State University
M. Kandemir , Pennsylvania State University
N. Vijaykrishnan , Pennsylvania State University
M. J. Irwin , Pennsylvania State University
Y. Xie , Pennsylvania State University
pp. 41-50
Session 2: Arithmetic I

Complex Square Root with Operand Prescaling (Abstract)

Milos D. Ercegovac , University of California at Los Angeles
Jean-Michel Muller , Ecole Normale Sup?rieure de Lyon, France
pp. 52-62

Parallel Montgomery Multipliers (Abstract)

Craig M. Chase , The University of Texas at Austin
Moboluwaji O. Sanu , The University of Texas at Austin
Earl E. Swartzlander, Jr. , The University of Texas at Austin
pp. 63-72

Improved-Throughput Networks of Basic On-Line Arithmetic Modules for DSP Applications (Abstract)

Alexandre F. Tenca , Oregon State University
Ajay C. Shantilal , Oregon State University
Mohammed H. Sinky , Oregon State University
pp. 73-83

Decimal Floating-Point Division Using Newton-Raphson Iteration (Abstract)

Michael J. Schulte , University of Wisconsin-Madison
Liang-Kai Wang , University of Wisconsin-Madison
pp. 84-95
Session 3: Instruction Set Extensions

A Public-Key Cryptographic Processor for RSA and ECC (Abstract)

Hans Eberle , Sun Microsystems Laboratories
Sheueling Chang Shantz , Sun Microsystems Laboratories
Nils Gura , Sun Microsystems Laboratories
Vipul Gupta , Sun Microsystems Laboratories
Shreyas Sundaram , University of Waterloo
Leonard Rarick , Sun Microsystems Laboratories
pp. 98-110

Architectural Support for Arithmetic in Optimal Extension Fields (Abstract)

Sandeep S. Kumar , Ruhr University Bochum, Germany
Johann Gro?sch?dl , IAIK, Graz University of Technology, Austria
Christof Paar , Ruhr University Bochum, Germany
pp. 111-124

Efficient Processing of Color Image Sequences Using a Color-Aware Instruction Set on Mobile Systems (Abstract)

D. Scott Wills , Georgia Institute of Technology, Atlanta
Jongmyon Kim , Georgia Institute of Technology, Atlanta
pp. 137-149
Session 4: (Special) Nanocomputing

Binary Multiplication based on Single Electron Tunneling (Abstract)

Sorin Cotofana , Delft University of Technology, The Netherlands
Casper Lageweg , Delft University of Technology, The Netherlands
Stamatis Vassiliadis , Delft University of Technology, The Netherlands
pp. 152-166
Session 5: Microarchitecture, Compilers and Optimization

Register Organization for Enhanced On-Chip Parallelism (Abstract)

Rama Sangireddy , University of Texas at Dallas, Richardson, TX
pp. 180-190

Design and Evaluation of a Network-Based Asynchronous Architecture for Cryptographic Devices (Abstract)

Ljiljana Dilparic , University of Edinburgh, UK
D. K. Arvind , University of Edinburgh, UK
pp. 191-201

Common Subexpression Elimination Involving Multiple Variables for Linear DSP Synthesis (Abstract)

Anup Hosangadi , University of California, Santa Barbara
Ryan Kastner , University of California, Santa Barbara
Farzan Fallah , Fujitsu Labs of America, Inc.
pp. 202-212

Optimizing the Memory Bandwidth with Loop Morphing (Abstract)

F. Catthoor , IMEC/ESAT KULeuven
L. Pinuel , DACYA UCM
S. Verdoorlaege , ESAT KULeuven
J. I. Gomez , DACYA UCM
P. Marchal , IMEC/ESAT KULeuven
pp. 213-223

Switching-Activity Minimization on Instruction-Level Loop Scheduling for VLIWDSP Applications (Abstract)

Zili Shao , University of Texas at Dallas
Edwin H.-M. Sha , University of Texas at Dallas
Meilin Liu , University of Texas at Dallas
Bin Xiao , University of Texas at Dallas
Qingfeng Zhuge , University of Texas at Dallas
pp. 224-234
Session 6: Arithmetic II

A Digit-Serial Algorithm for the Discrete Logarithm Modulo 2^k (Abstract)

David W. Matula , Southern Methodist University
Alex Fit-Florea , Southern Methodist University
pp. 236-246

Detecting Faults in Four Symmetric Key Block Ciphers (Abstract)

I. Koren , University of Massachusetts, Amherst
L. Breveglieri , Politecnico di Milano, Italy
Paolo Maistri , Politecnico di Milano, Italy
pp. 258-268

A Low-Power Carry Skip Adder with Fast Saturation (Abstract)

Suman Mamidi , Sandbridge Technologies, Inc., White Plains, NY; University of Wisconsin, Madison, WI
Stamatis Vassiliadis , Delft University of Technology, The Netherlands
John Glossner , Sandbridge Technologies, Inc., White Plains, NY
Michael J. Schulte , Sandbridge Technologies, Inc., White Plains, NY; University of Wisconsin, Madison, WI
Haoran Wang , Sandbridge Technologies, Inc., White Plains, NY
Pablo Balzola , Sandbridge Technologies, Inc., White Plains, NY
Kai Chirca , Sandbridge Technologies, Inc., White Plains, NY
pp. 269-279
Session 7: Communication, Interfaces and Memory

A Hierarchical Classification Scheme to Derive Interprocess Communication in Process Networks (Abstract)

Alexandru Turjan , Leiden Institute of Advanced Computer Science (LIACS), The Netherlands
Bart Kienhuis , Leiden Institute of Advanced Computer Science (LIACS), The Netherlands
Ed Deprettere , Leiden Institute of Advanced Computer Science (LIACS), The Netherlands
pp. 282-292

Efficient On-Chip Communications for Data-Flow IPs (Abstract)

Antoine Fraboulet , Citi, Insa-Lyon, France
Tanguy Risset , Inria, Lip, ENS-Lyon, France
pp. 293-303

Automatic Synthesis of Customized Local Memories for Multicluster Application Accelerators (Abstract)

Scott Mahlke , University of Michigan, Ann Arbor
Michael Chu , University of Michigan, Ann Arbor
Kevin Fan , University of Michigan, Ann Arbor
Manjunath Kudlur , University of Michigan, Ann Arbor
pp. 304-314

Optimized Data-Reuse in Processor Arrays (Abstract)

Renate Merker , Dresden University of Technology, Germany
Sebastian Siegel , Dresden University of Technology, Germany
pp. 315-325
Session 8: (Special) Reconfigurable Computing

Hyper-Programmable Architectures for Adaptable Networked Systems (Abstract)

Chidamber Kulkarni , Xilinx Research Laboratories
Eric Keller , Xilinx Research Laboratories
Gordon Brebner , Xilinx Research Laboratories
Phil James-Roxby , Xilinx Research Laboratories
pp. 328-338

Programming Transparency and Portable Hardware Interfacing: Towards General-Purpose Reconfigurable Computing (Abstract)

Laura Pozzi , Swiss Federal Institute of Technology Lausanne, Switzerland
Miljan Vuletic , Swiss Federal Institute of Technology Lausanne, Switzerland
Paolo Ienne , Swiss Federal Institute of Technology Lausanne, Switzerland
pp. 339-351
Session 9: Applications

Biosequence Similarity Search on the Mercury System (Abstract)

Joseph Lancaster , Washington University in St. Louis
Mark Franklin , Washington University in St. Louis
Jeremy Buhler , Washington University in St. Louis
Praveen Krishnamurthy , Washington University in St. Louis
Kwame Gyang , Washington University in St. Louis
Roger Chamberlain , Washington University in St. Louis
pp. 365-375

Stride Permutation Networks for Array Processors (Abstract)

Perttu Salmela , Tampere University of Technology, Finland
Jarmo Takala , Tampere University of Technology, Finland
Harri Sorokin , Tampere University of Technology, Finland
Tuomas J?rvinen , Tampere University of Technology, Finland
pp. 376-386

A Packet Scheduling Algorithm for IPSec Multi-Accelerator Based Systems (Abstract)

Alberto Ferrante , University of Milan
Vincenzo Piuri , University of Milan
Fabien Castanier , ST Microelectronics
pp. 387-397

Design of the QBIC Wearable Computing Platform (Abstract)

Oliver Amft , ETH Z?rich, Switzerland
Fabrizio Macaluso , ETH Z?rich, Switzerland
Stijn Ossevoort , ETH Z?rich, Switzerland
Michael Lauffer , ETH Z?rich, Switzerland
Paul Lukowicz , ETH Z?rich, Switzerland
Gerhard Tr?ster , ETH Z?rich, Switzerland
pp. 398-410

Author Index (PDF)

pp. 411-412
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