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Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004. (2004)
Galveston, Texas
Sept. 27, 2004 to Sept. 29, 2004
ISSN: 1063-6862
ISBN: 0-7695-2226-2
pp: 269-279
Michael J. Schulte , Sandbridge Technologies, Inc., White Plains, NY; University of Wisconsin, Madison, WI
Kai Chirca , Sandbridge Technologies, Inc., White Plains, NY
John Glossner , Sandbridge Technologies, Inc., White Plains, NY
Haoran Wang , Sandbridge Technologies, Inc., White Plains, NY
Suman Mamidi , Sandbridge Technologies, Inc., White Plains, NY; University of Wisconsin, Madison, WI
Pablo Balzola , Sandbridge Technologies, Inc., White Plains, NY
Stamatis Vassiliadis , Delft University of Technology, The Netherlands
ABSTRACT
In this paper, we present the design of a carry skip adder that achieves low power dissipation and high-performance operation. The carry skip adder's delay and power dissipation are reduced by dividing the adder into variable-sized blocks that balance the delay of inputs to the carry chain. This grouping reduces active power by minimizing extraneous glitches and transitions. Each block also uses highly optimized complementing carry look-ahead logic to reduce delay. Compared to previous designs, the adder architecture decreases power consumption by reducing the number of transistors, logic levels, and glitches. A 32-bit carry skip adder design that uses our approach has been implemented in 130nm CMOS technology. At 1.2V and 25C, the 32-bit adder has a critical path delay of 921ps and average power dissipation normalized to 600MHz operation of 0.786mW. We also present a technique to quickly perform saturating addition, which is useful in a variety of digital signal processing and multimedia applications. Our technique for fast saturation is based on techniques for carry select addition and works particularly well when the input and output operands can have different formats. A 40-bit carry skip adder that uses our technique for fast saturation has critical path delays of 1149ps in 130nm technology at 1.2V and 25C and 560ps in 90nm technology at 1.0V and 25C. The 40-bit adder's average power dissipation normalized to 600MHz operation is 0.928mW in 130nm technology and 0.335mW in 90nm technology.
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CITATION

S. Mamidi et al., "A Low-Power Carry Skip Adder with Fast Saturation," Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004.(ASAP), Galveston, Texas, 2004, pp. 269-279.
doi:10.1109/ASAP.2004.10038
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