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Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003 (2003)
The Hague, The Netherlands
June 24, 2003 to June 26, 2003
ISSN: 1063-6862
ISBN: 0-7695-1992-X
pp: 326
G. Dimitrakopoulos , Computer Engineering and Informatics Dept., University of Patras, 26500 Patras, Greece
H. T. Vergos , Computer Technology Institute, 3 Kolokotroni Str., 26221 Patras, Greece Computer Engineering and Informatics Dept., University of Patras, 26500 Patras, Greece
D. Nikolos , Computer Technology Institute, 3 Kolokotroni Str., 26221 Patras, Greece Computer Engineering and Informatics Dept., University of Patras, 26500 Patras, Greece
C. Efstathiou , Informatics Dept., TEI of Athens, 12210 Egaleo, Athens, Greece.
ABSTRACT
In this paper we at .rst reveal the cyclic nature of idempotency in the case of modulo 2<sup>n</sup> - 1 addition. Then based on this property, we derive for each n, a family of minimum logic depth modulo 2<sup>n</sup>- 1 adders, which allows several trade-offs between the number of operators, the internal wire length, and the fanout of internal nodes. Performance data, gathered using static CMOS implementations, reveal that the proposed architectures outperform all previously reported ones in terms of area and/or operation speed.
INDEX TERMS
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CITATION

G. Dimitrakopoulos, C. Efstathiou, D. Nikolos and H. T. Vergos, "A Family of Parallel-Pre.x Modulo 2n - 1 Adders," Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003(ASAP), The Hague, The Netherlands, 2003, pp. 326.
doi:10.1109/ASAP.2003.1212856
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