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2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors (2003)
The Hague, The Netherlands
June 24, 2003 to June 26, 2003
ISSN: 1063-6862
ISBN: 0-7695-1992-X
pp: 40
Anne-Claire Guillou , Irisa Campus de Beaulieu
Patrice Quinton , Irisa Campus de Beaulieu
Tanguy Risset , Inria, Lip, ENS-Lyon
ABSTRACT
This paper introduces some basic principles for extending the classical systolic synthesis methodology to multi-dimensional time. Multi-dimensional scheduling enables complex algorithms that do not admit linear schedules to be parallelized, but it also requires the use of memories in the architecture. We explain how to obtain compatible allocation and memory functions for vlsi (or simd-like code) generation. We also present an original mechanism for controlling a vlsi architecture that has a multi-dimensional schedule. A structural vhdl code has been derived and synthesized (for implementation on fpga platforms) using these systematic design principles. These results are preliminary steps to the hardware synthesis for multi-dimensional time.
INDEX TERMS
High-level synthesis, systolic architecture, multi-dimensional scheduling, fpga
CITATION
Anne-Claire Guillou, Patrice Quinton, Tanguy Risset, "Hardware Synthesis for Multi-Dimensional Time", 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors, vol. 00, no. , pp. 40, 2003, doi:10.1109/ASAP.2003.1212828
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