The Community for Technology Leaders
Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors (2002)
San Jose, California
July 17, 2002 to July 19, 2002
ISSN: 1063-6862
ISBN: 0-7695-1712-9
TABLE OF CONTENTS
Introduction
Keynote Presentation

Nanocomputing with Delays (PDF)

José A. B. Fortes , University of Florida
pp. 3
Session 1: Design Methodologies

A Compile Time Based Approach for Solving Out-of-Order Communication in Kahn Process Networks (Abstract)

Alexandru Turjan , Leiden Institute of Advanced Computer Science
Bart Kienhuis , Leiden Institute of Advanced Computer Science
Ed Deprettere , Leiden Institute of Advanced Computer Science
pp. 17

A Component Architecture for FPGA-Based, DSP System Design (Abstract)

Gary Spivey , University of Maryland and Rincon Research Corp.
Shuvra S. Bhattacharyya , University of Maryland
Kazuo Nakajima , University of Maryland and Nara Institute of Science and Technology
pp. 41
Session 2: Low Power Design

Low Power Memory Design (Abstract)

Wen-Tsong Shiue , Oregon State University
pp. 55

Reduced Power Consumption for MPEG Decoding with LNS (Abstract)

Mark G. Arnold , University of Manchester Institute of Science and Technology
pp. 65

A Model-Based Methodology for Application Specific Energy Efficient Data Path Design Using FPGAs (Abstract)

Sumit Mohanty , University of Southern California
Seonil Choi , University of Southern California
Ju-wook Jang , Sogang University
Viktor K. Prasanna , University of Southern California
pp. 76

Design Space Exploration for Energy-Efficient Secure Sensor Network (Abstract)

Lin Yuan , University of Maryland at College Park
Gang Qu , University of Maryland at College Park
pp. 88
Session 3: Computer Arithmetic I

High-Radix Logarithm with Selection by Rounding (Abstract)

J.-A. Piñeiro , University Santiago de Compostela
M. D. Ercegovac , University of California at Los Angeles
J. D. Bruguera , University Santiago de Compostela
pp. 101

An Analysis of the CORDIC Algorithm for Direct Digital Frequency Synthesis (Abstract)

Chang Yong Kang , University of Texas at Austin
Earl E. Swartzlander, Jr. , University of Texas at Austin
pp. 111

Evaluating Products of Non Linear Functions by Indirect Bipartite Table Lookup (Abstract)

David W. Matula , Southern Methodist University
Alex Fit-Florea , Southern Methodist University
Lee D. McFearin , Southern Methodist University
pp. 120
Session 4: Memory Organization

Predictable Instruction Caching for Media Processors (Abstract)

J. Irwin , University of Bristol
M. D. May , University of Bristol
H. L. Muller , University of Bristol
D. Page , University of Bristol
pp. 141

A Mathematical Model of Trace Cache (Abstract)

Afzal Hossain , Nanova Corporation
Daniel J. Pease , Syracuse University
James S. Burns , Intel Corporation
Nasima Parveen , Intel Corporation
pp. 151

Implementation of a 32-bit RISC Processor for the Data-Intensive Architecture Processing-In-Memory Chip (Abstract)

Jeffrey Draper , University of Southern California
Jeff Sondeen , University of Southern California
Sumit Mediratta , University of Southern California
I. Kim , University of Southern California
pp. 163

A Mid-Texturing Pixel Rasterization Pipeline Architecture for 3D Rendering Processors (Abstract)

Woo-Chan Park , Yonsei University
Kil-Whan Lee , Yonsei University
Il-San Kim , Yonsei University
Tack-Don Han , Yonsei University
Sung-Bong Yang , Yonsei University
pp. 173
Session 5: Computer Arithmetic II

Fast Radix-4 Retimed Division with Selection by Comparisons (Abstract)

Elisardo Antelo , Universidade de Santiago
Tomás Lang , University of California at Irvine
Paolo Montuschi , Politecnico di Torino
Alberto Nannarelli , Università di Roma "Tor Vergata"
pp. 185

Reviewing 4-to-2 Adders for Multi-Operand Addition (Abstract)

Peter Kornerup , Southern Danish University
pp. 218
Session 6: Media Processors

Design and Evaluation of a Multimedia Computing Architecture Based on a 3D Graphics Pipeline (Abstract)

ChrisY. Chung , University of Washington
RaviA. Managuli , University of Washington
Yongmin Kim , University of Washington
pp. 243

Refining Instruction Set Architecture for High-Performance Multimedia Processing in Constrained Environments (Abstract)

Ruby B. Lee , Princeton University
A. Murat Fiskiran , Princeton University
Zhijie Shi , Princeton University
Xiao Yang , Princeton University
pp. 253

Polynomial Evaluation on Multimedia Processors (Abstract)

Julio Villalba , University of Malaga
Gerardo Bandera , University of Malaga
Mario A. Gonzalez , University of Malaga
Javier Hormigo , University of Malaga
Emilio L. Zapata , University of Malaga
pp. 265
Session 7: Cryptography

Integrated Design of AES (Advanced Encryption Standard) Encrypter and Decrypter (Abstract)

Chih-Chung Lu , Industrial Technology Research Institute
Shau-Yin Tseng , Industrial Technology Research Institute
pp. 277

Instruction Stream Mutation for Non-Deterministic Processors (Abstract)

J. Irwin , University of Bristol
D. Page , University of Bristol
N. P. Smart , University of Bristol
pp. 286

A Novel Pipelined Threads Architecture for AES Encryption Algorithm (Abstract)

Mehboob Alam , University of Calgary
Wael Badawy , University of Calgary
Graham Jullien , University of Calgary
pp. 296

On the Propagation of Faults and Their Detection in a Hardware Implementation of the Advanced Encryption Standard (Abstract)

Guido Bertoni , Politecnico Di Milano
Luca Breveglieri , Politecnico Di Milano
Israel Koren , University of Massachusetts at Amherst
Paolo Maistri , Politecnico Di Milano
Vincenzo Piuri , University of Milan
pp. 303
Session 8: VLSI Architectures

Matrix Engine for Signal Processing Applications Using the Logarithmic Number System (Abstract)

E. I. Chester , University of Newcastle upon Tyne
J. N. Coleman , University of Newcastle upon Tyne
pp. 315

A VLSI Architecture for Object Recognition Using Tree Matching (Abstract)

K. Sitaraman , University of South Florida
N. Ranganathan , University of South Florida
A. Ejnioui , University of Central Florida
pp. 325

Optical Network Reconfiguration for Signal Processing Applications (Abstract)

Roger Chamberlain , Washington University at St. Louis
Mark Franklin , Washington University at St. Louis
Praveen Krishnamurthy , Washington University at St. Louis
pp. 344
Session 9: Application-Specific System Design

New Results on Array Contraction (Abstract)

Alain Darte , Laboratoire de l éInformatique du Parallélisme
Guillaume Huard , Laboratoire de l éInformatique du Parallélisme
pp. 359

A CORBA-Based GIS-T for Ambulance Assignment (Abstract)

Tsai-Yun Liao , Chaoyang University of Technology
Ta-Yin Hu , Feng Chi University
pp. 371

Advances in Bit Width Selection Methodology (Abstract)

David Cachera , Irisa/ENS-Cachan
Tanguy Risset , Inria/Lip
pp. 381

Tradeoffs Between Quality of Results and Resource Consumption in a Recognition System (Abstract)

Michael DeVore , Washington University at St. Louis
Roger Chamberlain , Washington University at St. Louis
George Engel , Southern Illinois University at Edwardsville
Joseph O?Sullivan , Washington University at St. Louis
Mark Franklin , Washington University at St. Louis
pp. 391
Author Index

Author Index (PDF)

pp. 403
82 ms
(Ver 3.3 (11022016))