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Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors (2000)
Boston, Massachusetts
July 10, 2000 to July 12, 2000
ISSN: 1063-6862
ISBN: 0-7695-0716-6
TABLE OF CONTENTS
Keynote
Video and Multimedia Processors, Chair: Jürgen Teich, Paderborn University

Architecture of an Image Rendering Co-Processor for MPEG-4 Systems (Abstract)

M. Berekovic , Universit?t Hannover
P. Pirsch , Universit?t Hannover
K. -I Wels , ENST
C. Miro , Infineon
A. Lafage , Infineon
C. Heer , CSELT
G. Ghigo , CSELT
pp. 15

A Multiplication-Free Parallel Architecture for Affine Transformation (Abstract)

Wael Badawy , University of Louisiana
Magdy Bayoumi , University of Louisiana
pp. 25

A Simple RISC Microprocessor Core Designed for Digital Set-Top-Box Applications (Abstract)

M. Dal Poz , University of Sao Paulo
J. Aedo Cobo , University of Sao Paulo
W. Van Noije , University of Sao Paulo
M. Zuffo , University of Sao Paulo
pp. 35
Reconfigurable Computing, Chair: Doran Wilde, Brigham Young University

Formal Verification for Microprocessors with Extendable Instruction Set (Abstract)

Sergej Sawitzki , Dresden University of Technology
Rainer G. Spallek , Dresden University of Technology
Jens Schönherr , Fraunhofer-Institut Integrierte Schaltungen
Bernd Straube , Fraunhofer-Institut Integrierte Schaltungen
pp. 47

Compiling Image Processing Applications to Reconfigurable Hardware (Abstract)

Robert Rinker , Colorado State University
Jeff Hammes , Colorado State University
Walid A. Najjar , Colorado State University
Wim Böhm , Colorado State University
Bruce Draper , Colorado State University
pp. 56

Integration of High-Performance ASICs into Reconfigurable Systems Providing Additional Multimedia Functionality (Abstract)

Holger Blume , University of Technology RWTH Aachen
Hans-Martin Blüthgen , University of Technology RWTH Aachen
Christiane Henning , University of Technology RWTH Aachen
Patrick Osterloh , University of Technology RWTH Aachen
pp. 66
Modeling and Synthesis, Chair: Shuvra Bhattacharyya, University of Maryland at College Park

High Level Modeling for Parallel Executions of Nested Loop Algorithms (Abstract)

Ed F. Deprettere , Leiden University
Edwin Rijpkema , Leiden University
Paul Lieverse , Delft University of Technology
Bart Kienhuis , University of California at Berkeley
pp. 79

High-Level Synthesis of Nonprogrammable Hardware Accelerators (Abstract)

Robert Schreiber , Hewlett-Packard Company
Shail Aditya , Hewlett-Packard Company
B. Ramakrishna Rau , Hewlett-Packard Company
Vinod Kathail , Hewlett-Packard Company
Scott Mahlke , Hewlett-Packard Company
Santosh Abraham , Hewlett-Packard Company
Greg Snider , Hewlett-Packard Company
pp. 113
Cryptography, Chair: Ruby Lee, Princeton University

Implementing 1,024-Bit RSA Exponentiation on a 32-Bit Processor Core (Abstract)

B.J. Phillips , University of Adelaide
N. Burgess , Cardiff University
pp. 127

Bit Permutation Instructions for Accelerating Software Cryptography (Abstract)

Zhijie Shi , Princeton University
Ruby B. Lee , Princeton University
pp. 138

Performance-Scalable Array Architectures for Modular Multiplication (Abstract)

William L. Freking , University of Minnesota
Keshab K. Parhi , University of Minnesota
pp. 149
Digital Signal Processing, Chair: Joseph Cavallaro, Rice University

A 108 Gbps, 1.5 GHz 1D-DCT Architecture (Abstract)

Ahmed Shams , University of Louisiana at Lafayette
Magdy Bayoumi , University of Louisiana at Lafayette
pp. 163

A 550 Mb/s Radix-4 Bit-level Pipelined 16-State 0.25-?m CMOS Viterbi Decoder (Abstract)

V.S. Gierenz , Institute of Technology RWTH Aachen
O. Weiss , Institute of Technology RWTH Aachen
T.G. Noll , Institute of Technology RWTH Aachen
I. Carew , Infineon Technologies
J. Ashley , Infineon Technologies
R. Karabed , Infineon Technologies
pp. 195
Arithmetic,Chair: Magdy Bayoumi, University of Louisiana

A Hardware Algorithm for Variable-Precision Logarithm (Abstract)

Javier Hormigo , University of Malaga
Julio Villalba , University of Malaga
Michael J. Schulte , Lehigh University
pp. 215

Block-Update Parallel Processing QRD-RLS Algorithm for Throughput Improvement with Low Power Consumption (Abstract)

Lijun Gao , University of Minnesota in Twin Cities
Keshab K. Parhi , University of Minnesota in Twin Cities
pp. 225

A 16-Bit x 16-Bit MAC Design Using Fast 5:2 Compressors (Abstract)

Ohsang Kwon , University of Texas at Austin
Earl E. Swartzlander , University of Texas at Austin
Kevin Nowka , IBM Austin Research Lab
pp. 235
Multiprocessor Systems, Chair: Ed Deprettere, Leiden University

Control for High-Speed PE Arrays (Abstract)

Martin C. Herbordt , University of Houston
Honghai Zhang , University of Houston
Calvin Lin , University of Houston
Hong Rao , University of Houston
Jade Cravy , GDA Technologies
pp. 247

Explicit SIMD Programming for Asynchronous Applications (Abstract)

Andrea Di Blas , University of California at Santa Cruz
Richard Hughey , University of California at Santa Cruz
pp. 258

Quadratic Control Signals in Linear Systolic Arrays (Abstract)

Scott Bowden , Brigham Young University
Doran Wilde , Brigham Young University
pp. 268

Contention-Conscious Transaction Ordering in Embedded Multiprocessors (Abstract)

Mukul Khandelia , University of Maryland at College Park
Shuvra S. Bhattacharyya , University of Maryland at College Park
pp. 276
Application-Specific Architectures, Chair: Neil Burgess, Cardiff University

Architecture for Wavelet Packet Transform with Best Tree Searching (Abstract)

Maria A. Trenas , University of Malaga
Juan López , University of Malaga
Manuel Sánchez , University of Malaga
Emilio L. Zapata , University of Malaga
Francisco Argüello , University of Santiago
pp. 289

Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter (Abstract)

Marcus Bednara , University of Paderborn
Oliver Beyer , University of Paderborn
Juergen Teich , University of Paderborn
Rolf Wanka , University of Paderborn
pp. 299
Design Methodology, Chair: Elias Manolakos

Partitioning Conditional Data Flow Graphs for Embedded System Design (Abstract)

M. Auguin , Universit? de Nice Sophia Antipolis
L. Bianco , Universit? de Nice Sophia Antipolis
L. Capella , Philips Semiconductors Sophia
E. Gresset , Philips Semiconductors Sophia
pp. 339

Generation of Scheduling Functions Supporting LSGP-Partitioning (Abstract)

Dirk Fimmel , Dresden University of Technology
pp. 349

Author Index (PDF)

pp. 359
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