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2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors (1997)
Zurich, SWITZERLAND
July 14, 1997 to July 16, 1997
ISSN: 1063-6862
ISBN: 0-8186-7958-1
TABLE OF CONTENTS
Keynote

A Visual Computing Environment for Very Large Scale Biomolecular Modeling (Abstract)

R. Sharma , Pennsylvania State University
Z. Lo , Beckman Institute for Advanced Science and Technology University of Illinois at Urbana-Champaign
A. Dalke , Beckman Institute for Advanced Science and Technology University of Illinois at Urbana-Champaign
W. Humphrey , Beckman Institute for Advanced Science and Technology University of Illinois at Urbana-Champaign
V.I. Pavlovic , Beckman Institute for Advanced Science and Technology University of Illinois at Urbana-Champaign
K. Schulten , Beckman Institute for Advanced Science and Technology University of Illinois at Urbana-Champaign
J.C. Phillips , Beckman Institute for Advanced Science and Technology University of Illinois at Urbana-Champaign
M. Zeller , Beckman Institute for Advanced Science and Technology University of Illinois at Urbana-Champaign
Y. Zhao , Beckman Institute for Advanced Science and Technology University of Illinois at Urbana-Champaign
S. Chu , Beckman Institute for Advanced Science and Technology University of Illinois at Urbana-Champaign
T.S. Huang , Beckman Institute for Advanced Science and Technology University of Illinois at Urbana-Champaign
pp. 3
Regular Architectures

On Computing With Locally-Interconnected Architectures in Atomic/Nanoelectronic Systems (Abstract)

Vwani P. Roychowdhury , University of California, Los Angeles
M. P. Anantram , University of California, Los Angeles
pp. 14

Realization of a nonlinear digital filter on a DSP array processor (Abstract)

E.J. Powers , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
E.E. Swartzlander, Jr. , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
H. Kwan , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 24

A Linear Array Parallel Image Processor: SliM-II (Abstract)

Myung H. Sunwoo , Ajou University
Hyunman Chang , Ajou University
Soohwan Ong , Ajou University
pp. 34

A massively parallel implementation of the watershed based on cellular automata (Abstract)

D. Noguet , CEA, Centre d'Etudes Nucleaires, de Grenoble, France
pp. 42

A strategy for determining a Jacobi specific dataflow processor (Abstract)

E. Rijpkema , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
E.F. Deprettere , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
Jun Ma , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
G. Hekstra , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 53
Special Session: Architectures for Video Coding, Organizers: L. Chen, P. Pirsch

Buffer size optimization for full-search block matching algorithms (Abstract)

Yuan-Hau Yeh , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Chen-Yi Lee , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 76

A flexible data-interlacing architecture for full-search block-matching algorithm (Abstract)

Yung-Pin Lee , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Liang-Gee Chen , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Yeong-Kang Lai , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
pp. 96
Arithmetic

New arithmetic coder/decoder architectures based on pipelining (Abstract)

R.R. Osorio , Dept. of Electron. & Comput., Santiago de Compostela Univ., Spain
J.D. Bruguera , Dept. of Electron. & Comput., Santiago de Compostela Univ., Spain
pp. 106

Processor Elements for the Standard Cell Implementation of Residue Number Systems (Abstract)

A. Drolshagen , Institute for Microelectronics, FB1, University of Bremen,
W. Anheier , Institute for Microelectronics, FB1, University of Bremen,
H. Henkelmann , Institute for Microelectronics, FB1, University of Bremen,
pp. 116

Low latency word serial CORDIC (Abstract)

J. Villalba , Dept. Comput. Archit., Malaga Univ., Spain
T. Lang , Dept. Comput. Archit., Malaga Univ., Spain
pp. 124

CORDIC-based computation of arccos and arcsin (Abstract)

Elisardo Antelo , Universidade de Santiago de Compostela
Tomas Lang , University of California at Irvine
pp. 132

Low Power CORDIC Implementation Using Redundant Number Representation (Abstract)

Josef A. Nossek , Munich University of Technology
Sven Simon , Munich University of Technology
Christian V. Schimpfle , Munich University of Technology
pp. 154
Keynote

Architectural approaches for video compression (Abstract)

P. Pirsch , Lab. fur Informationstechnol., Hannover Univ., Germany
H.-J. Stolberg , Lab. fur Informationstechnol., Hannover Univ., Germany
pp. 176
Array Synthesis

Three-dimensional orthogonal tile sizing problem : mathematical programming approach (Abstract)

H. Bourzoufi , LIMAV, Valenciennes Univ., France
R. Andonov , LIMAV, Valenciennes Univ., France
N. Yanev , LIMAV, Valenciennes Univ., France
pp. 209

Libraries of schedule-free operators in Alpha (Abstract)

F. de Dinechin , IRISA, Rennes, France
pp. 239
Special Session: Mapping Models of Computation to Architectures, Organizers: E. Deprettere, B. Evans, K. Vissers

Optimized software synthesis for synchronous dataflow (Abstract)

P.K. Murthy , Hitachi America Ltd., Brisbane, CA, USA
E.A. Lee , Hitachi America Ltd., Brisbane, CA, USA
S.S. Bhattacharyya , Hitachi America Ltd., Brisbane, CA, USA
pp. 250

The Processing Graph Method Tool (PGMT) (Abstract)

Richard S. Stevens , Naval Research Laboratory
pp. 263

Algorithm and architecture-level design space exploration using hierarchical data flows (Abstract)

H.P. Peixoto , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
M.F. Jacome , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 272

Mapping multirate dataflow to complex RT level hardware models (Abstract)

J. Horstmannshoff , Integrated Syst. for Signal Process., Aachen Univ. of Technol., Germany
H. Meyr , Integrated Syst. for Signal Process., Aachen Univ. of Technol., Germany
T. Grotker , Integrated Syst. for Signal Process., Aachen Univ. of Technol., Germany
pp. 283
Design Methodology I

Heterogeneous Multiprocessor Scheduling and Allocation using Evolutionary Algorithms (Abstract)

M. Schwiegershausen , Universitat Hannover
C. Reuter , Universitat Hannover
P. Pirsch , Universitat Hannover
pp. 294

Performance model of the Argonne Voyager multimedia server (Abstract)

R. Olson , Div. of Math. & Comput. Sci., Argonne Nat. Lab., IL, USA
T. Disz , Div. of Math. & Comput. Sci., Argonne Nat. Lab., IL, USA
R. Stevens , Div. of Math. & Comput. Sci., Argonne Nat. Lab., IL, USA
pp. 316

Automatic data mapping of signal processing applications (Abstract)

D. Barthou , Ecole de Mines de Paris, Fontainebleau, France
C. Ancourt , Ecole de Mines de Paris, Fontainebleau, France
B. Jeannet , Ecole de Mines de Paris, Fontainebleau, France
C. Guettier , Ecole de Mines de Paris, Fontainebleau, France
F. Irigoin , Ecole de Mines de Paris, Fontainebleau, France
J. Mattioli , Ecole de Mines de Paris, Fontainebleau, France
J. Jourdan , Ecole de Mines de Paris, Fontainebleau, France
pp. 350
Keynote

Configurable computing: the catalyst for high-performance architectures (Abstract)

C. Ebeling , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
D.C. Cronquist , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
P. Franklin , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
pp. 0364
Systems and Applications

Fast Arithmetic and Fault Tolerance in the FERMI System (Abstract)

Luigi Dadda , Dipartimento di Elettronica e Informazione - Politecnico di Milan0
Luca Breveglieri , Dipartimento di Elettronica e Informazione - Politecnico di Milan0
Vincenzo Piuri , Dipartimento di Elettronica e Informazione - Politecnico di Milan0
pp. 374

A Novel Sequencer Hardware for Application Specific Computing (Abstract)

Ulrich Nageldinger , University of Kaiserslautern
Michael Herz , University of Kaiserslautern
Reiner W. Hartenstein , University of Kaiserslautern
Jürgen Becker , University of Kaiserslautern
pp. 392

A FPGA-based Implementation of an Intravenous Infusion Controller System (Abstract)

Marcus V.D. dos Santos , Depto. de Informatica-UFPE
Cristiano C. de Araujo , Depto. de Informatica-UFPE
Edna Barros , Depto. de Informatica-UFPE
pp. 402

Conception and design of a RISC CPU for the use as embedded controller within a parallel multimedia architecture (Abstract)

D. Mlynek , Ecole Polytech. Federale de Lausanne, Switzerland
S. Dogimont , Ecole Polytech. Federale de Lausanne, Switzerland
A. Torielli , Ecole Polytech. Federale de Lausanne, Switzerland
F. Mombers , Ecole Polytech. Federale de Lausanne, Switzerland
M. Gumm , Ecole Polytech. Federale de Lausanne, Switzerland
pp. 412

A dedicated circuit for charged particles simulation using the Monte Carlo method (Abstract)

A. Guyot , Lab. de Phys. des Composants a Semicond., ENSERG, Grenoble, France
J. Zimmermann , Lab. de Phys. des Composants a Semicond., ENSERG, Grenoble, France
A. Negoi , Lab. de Phys. des Composants a Semicond., ENSERG, Grenoble, France
pp. 422

A Modular Element for Shared Buffer ATM Switch Fabrics (Abstract)

Mike Parks , Motorola Fast Static RAM Division
pp. 432
Special Session: Design Methodology II, Organizer: G. Fettweis

On core and more: a design perspective for systems-on-a-chip (Abstract)

V. Zivojnovic , Integrated Syst. for Signal Process., Aachen Univ. of Technol., Germany
H. Meyr , Integrated Syst. for Signal Process., Aachen Univ. of Technol., Germany
S. Pees , Integrated Syst. for Signal Process., Aachen Univ. of Technol., Germany
M. Vaupel , Integrated Syst. for Signal Process., Aachen Univ. of Technol., Germany
pp. 448

ADPCM codec: from system level description to versatile HDL model (Abstract)

J. Stahl , Synopsys Inc., Herzogenrath, Germany
K.-J. Koch , Synopsys Inc., Herzogenrath, Germany
H. Dawid , Synopsys Inc., Herzogenrath, Germany
pp. 458

Design methodology for digital signal processing (Abstract)

G. Fettweis , Tech. Univ. Dresden, Germany
pp. 468
Image Processing and Filtering

A flexible VLSI architecture for variable block size segment matching with luminance correction (Abstract)

A. Weisgerber , Tech. Univ. Munchen, Germany
P.M. Kuhn , Tech. Univ. Munchen, Germany
R. Poppenwimmer , Tech. Univ. Munchen, Germany
W. Stechele , Tech. Univ. Munchen, Germany
pp. 479

An efficient architecture for the in place fast cosine transform (Abstract)

M. Sanchez , Dept. of Comput. Archit., Malaga Univ., Spain
O. Plata , Dept. of Comput. Archit., Malaga Univ., Spain
J. Lopez , Dept. of Comput. Archit., Malaga Univ., Spain
E.L. Zapata , Dept. of Comput. Archit., Malaga Univ., Spain
pp. 499

An efficient video decoder design for MPEG-2 MP@ML (Abstract)

Nam Ling , Dept. of Comput. Eng., Santa Clara Univ., CA, USA
Jui-Hua Li , Dept. of Comput. Eng., Santa Clara Univ., CA, USA
pp. 509

Discrete Lagrangian Method for Optimizing the Design of Multiplierless QMF Filter Banks (Abstract)

Yi Shang , University of Illinois at Urbana-Champaign
Benjamin W. Wah , University of Illinois at Urbana-Champaign
Zhe Wu , University of Illinois at Urbana-Champaign
pp. 529

Index of Authors (PDF)

pp. 539
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