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Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors (1997)
Zurich, SWITZERLAND
July 14, 1997 to July 16, 1997
ISSN: 1063-6862
ISBN: 0-8186-7958-1
pp: 374
Luca Breveglieri , Dipartimento di Elettronica e Informazione - Politecnico di Milan0
Luigi Dadda , Dipartimento di Elettronica e Informazione - Politecnico di Milan0
Vincenzo Piuri , Dipartimento di Elettronica e Informazione - Politecnico di Milan0
ABSTRACT
The FERMI is a data acquisition system for calorimetry experiments in high energy physics at the LHC, CERN. The system contains a large number of acquisition channels, with a precision of 16 bits and a sampling rate of 40 MHZ. A large part of the information driven by the channels is processed locally, to reduce the amount of data. This requires to cluster several channels by adding them. The paper presents the design of a fast, low cost adder chip, based on the implementation of column compression techniques, for the computation of integer addition. Since the system is operating in a radiation-hard environment, fault tolerance (namely fault detection) is implemented by means of arithmetic code.
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CITATION

L. Dadda, L. Breveglieri and V. Piuri, "Fast Arithmetic and Fault Tolerance in the FERMI System," Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors(ASAP), Zurich, SWITZERLAND, 1997, pp. 374.
doi:10.1109/ASAP.1997.606842
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