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Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors (1997)
Zurich, SWITZERLAND
July 14, 1997 to July 16, 1997
ISSN: 1063-6862
ISBN: 0-8186-7958-1
pp: 86
ABSTRACT
This paper presents a circuit dedicated to real time geometrical transforms of pictures. The supported transforms are third degree polynomials of two variables. The post-processing is performed by a bilinear filter. An embedded DSP core is in charge of high level, low rate, control tasks while a set of hard wired units is in charge of computing intensive low level tasks.
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CITATION

C. Miro, V. Paquet, R. Pacalet and N. Darbel, "A VLSI Architecture for Image Geometrical Transformations Using an Embedded Core Based Processor," Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors(ASAP), Zurich, SWITZERLAND, 1997, pp. 86.
doi:10.1109/ASAP.1997.606815
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