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2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors (1996)
Chicago, IL
Aug. 19, 1996 to Aug. 23, 1996
ISSN: 1063-6862
ISBN: 0-8186-7542-X
TABLE OF CONTENTS
Miscellaneous Applications, Chair: Jean-Michel Muller

An Architectural Design For Parallel Fractal Compression (Abstract)

M.J. Irwin , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
H.N. Kim , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
R.M. Owens , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
K.P. Acken , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
pp. 3

A Decomposition Method For Efficient Use Of Distributed Supercomputers For Finite Element Applications (Abstract)

V.E. Taylor , Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
J. Chen , Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
R. Stevens , Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
T. Canfield , Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
pp. 12

Kestrel: A Programmable Array for Sequence Analysis (Abstract)

Kevin Karplus , karplus@cse.ucsc.edu
Richard Hughey , rph@cse.ucsc.edu
Don Speck , University of California, Santa Cruz, CA 95064
Jeffrey D. Hirschberg , hirsch@cse.ucsc.edu
pp. 25

Finite Word-Length Effects Of An Unified Systolic Array For 2-D DCT/IDCT (Abstract)

C. Yim , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
E.E. Swartzlander, Jr. , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
H. Lim , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 35
Arithmetic Algorithms and Architectures, Chair: Luigi Dadda

A New Euclidean Division Algorithm For Residue Number Systems (Abstract)

J.-C. Bajard , Univ. de Provence, Marseille, France
L.-S. Didier , Univ. de Provence, Marseille, France
J.-M. Muller , Univ. de Provence, Marseille, France
pp. 45

Radix-4 Vectoring Cordic Algorithm And Architectures (Abstract)

J.D. Bruguera , Dept. Comput. Archit., Malaga Univ., Spain
E. Antelo , Dept. Comput. Archit., Malaga Univ., Spain
J.C. Arrabal , Dept. Comput. Archit., Malaga Univ., Spain
E.L. Zapata , Dept. Comput. Archit., Malaga Univ., Spain
J. Villalba , Dept. Comput. Archit., Malaga Univ., Spain
pp. 55

Architectural Optimizations For A Floating Point Multiply-Accumulate Unit In A Graphics Pipeline (Abstract)

A.K. Garga , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
M.J. Irwin , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
K.P. Acken , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
R.M. Owens , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
pp. 65

Efficient Finite Field Serial/Parallel Multiplication (Abstract)

L. Song , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
K.K. Parhi , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
pp. 72

Plenary Session (PDF)

pp. null
Keynote Address
DSP Architectures, Chair: Arup Gupta

Area-Efficient Parallel FIR Digital Filter Implementations (Abstract)

David A. Parker , Department of Electrical Engineering University of Minnesota
Keshab K. Parhi , Department of Electrical Engineering University of Minnesota
pp. 93

A Novel Matching Criterion And Low Power Architecture For Real-Time Block Based Motion Estimation (Abstract)

Y.H. Hu , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
H. Yeo , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
pp. 122
Systolic Algorithms and Architectures, Chair: S.Y. Kung

Scheduling of Partitioned Regular Algorithms on Processor Arrays with Constrained Resources (Abstract)

Jurgen Teich , Institute TIK ETH Zurich, Gloriastrasse 35 CH-8092 Zurich, Switzerland
Lothar Thiele , Institute TIK ETH Zurich, Gloriastrasse 35 CH-8092 Zurich, Switzerland
Li Zhang , Institute TIK ETH Zurich, Gloriastrasse 35 CH-8092 Zurich, Switzerland
pp. 131

Automatic Generation of Modular Mappings (Abstract)

Hyuk-Jae Lee , Purdue University {hyuk,fortes}@ecn.purdue.edu
Jose A.B. Fortes , Purdue University {hyuk,fortes}@ecn.purdue.edu
pp. 155

High-Speed Viterbi Decoder: An Efficient Scheduling Method to Exploit the Pipelining (Abstract)

J.D. Bruguera , Univ. Santiago de Compostela elmboo@usc.es
M. Boo , Univ. Santiago de Compostela elmboo@usc.es
E.L. Zapata , Univ. Santiago de Compostela elmboo@usc.es
F. Arguello , Univ. Santiago de Compostela elmboo@usc.es
pp. 165
Poster Session, Chair: Roger Woods

Parallel Algorithm And Architecture For Two-Step Division-Free Gaussian Elimination (Abstract)

S. Peng , Aizu Univ., Fukushima, Japan
I. Sedukhin , Aizu Univ., Fukushima, Japan
S. Sedukhin , Aizu Univ., Fukushima, Japan
pp. 183

A Common Architecture For The DWT and IDWT (Abstract)

R.M. Owens , Comput. Sci. Lab., Xerox Palo Alto Res. Center, CA, USA
M. Vishwanath , Comput. Sci. Lab., Xerox Palo Alto Res. Center, CA, USA
pp. 193

Overcoming chip-to-chip delays and clock skews (Abstract)

A. Litman , Fachbereich Inf., Saarlandes Univ., Saarbrucken, Germany
G. Even , Fachbereich Inf., Saarlandes Univ., Saarbrucken, Germany
pp. 199

A VLSI System Architecture For Real-Time Intelligent Decision Making (Abstract)

N. Ranganathan , Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
M.I. Patel , Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
pp. 221

Microphone Array for Hearing Aid and Speech Enhancement Applications (Abstract)

D. Korompis , Electrical Engineering Dept. UCLA, Los Angeles, CA 90095-1594
A. Wang , Electrical Engineering Dept. UCLA, Los Angeles, CA 90095-1594
S. Gao , House Ear Institute Los Angeles,CA 90057
F. Lorenzelli , Electrical Engineering Dept. UCLA, Los Angeles, CA 90095-1594
S. Soli , House Ear Institute Los Angeles,CA 90057
K. Yao , Electrical Engineering Dept. UCLA, Los Angeles, CA 90095-1594
R.E. Hudson , Electrical Engineering Dept. UCLA, Los Angeles, CA 90095-1594
pp. 231

Design of the Distributed Architecture of a Machine-tool Using FIP Fieldbus (Abstract)

Francis LePage , Centre de Recherche en Automatique de Nancy Universite de Nancy I, BP239, 54506 Vandoeuvre-les-Nancy cedex, France
Daping Song , Centre de Recherche en Automatique de Nancy Universite de Nancy I, BP239, 54506 Vandoeuvre-les-Nancy cedex, France
Thierry Divoux , Centre de Recherche en Automatique de Nancy Universite de Nancy I, BP239, 54506 Vandoeuvre-les-Nancy cedex, France
pp. 250
Panel
Design Methodologies, Chair: Tobias G. Nell

NULL Convention Logic/sup TM/: A Complete And Consistent Logic For Asynchronous Digital Circuit Synthesis (Abstract)

S.A. Brandt , Theseus Logic Inc., St. Paul, MN, USA
K.M. Fant , Theseus Logic Inc., St. Paul, MN, USA
pp. 261

A Synthesis System For Bus-Based Wavefront Array Architectures (Abstract)

U. Nageldinger , Kaiserslautern Univ., Germany
J. Becker , Kaiserslautern Univ., Germany
R. Kress , Kaiserslautern Univ., Germany
M. Herz , Kaiserslautern Univ., Germany
R.W. Hartenstein , Kaiserslautern Univ., Germany
pp. 274

Hardware Synthesis From Encapsulated Verilog Modules (Abstract)

D.R. Smith , Dept. of Comput. Sci., State Univ. of New York, Stony Brook, NY, USA
pp. 284
Rapid Prototyping, Chair: Robert Owens

Reconfigurable Processing With Field Programmable Gate Arrays (Abstract)

J. Watson , Xilinx Inc., San Jose, CA, USA
B.K. Fawcett , Xilinx Inc., San Jose, CA, USA
pp. 293

Rapid Prototyping of Reconfigurable Coprocessors (Abstract)

Madhavi Vootukuru , University of Cincinnati
Jeff Walrath , University of Cincinnati
Sriram Govindarajan , University of Cincinnati
Vinoo Srinivasan , University of Cincinnati
Ranga Vemuri , University of Cincinnati
Naren Narasimhan , University of Cincinnati
pp. 303

Jacobi-Specific Processor Arrays (Abstract)

G.J. Hekstra , Philips Components, Eindhoven, Netherlands
H.W. Van Dijk , Philips Components, Eindhoven, Netherlands
E.F. Deprettere , Philips Components, Eindhoven, Netherlands
pp. 323
Compilers I, Chair: Kung Yao

Latency-constrained Resynchronization for Multiprocessor DSP Implementation (Abstract)

E. A. Lee , University of California at Berkeley eal@eecs.berkeley.edu, fax: (510)642-2739.
S. Sriram , DSP R&D Center, Texas Instruments Incorporated sriram@hc.ti.com
S. S. Bhattacharyya , Semiconductor Research Laboratory, Hitachi America, Ltd. shuvra@halsrl.com
pp. 365
Compilers II, Chair: Sayfe Kiaei

On Supernode Transformation with Minimized Total Running Time (Abstract)

Edin Hodzic , HaL Computer Systems ehodzic@scu.edu
Weijia Shang , Santa Clara University wshang@scus19.scu.edu
pp. 402

Index of Authors (PDF)

pp. 425
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