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2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors (1995)
Strasbourg, France
July 24, 1995 to July 26, 1995
ISSN: 1063-6862
ISBN: 0-8186-7109-2
TABLE OF CONTENTS
Opening Session, Chair: P. Cappello
Session 1: Scheduling and Mapping, Chair: J. Teich

The naive execution of affine recurrence equations (Abstract)

D. Wilde , Dept. of Comput. Sci., Oregon State Univ., Corvallis, OR, USA
S. Rajopadhye , Dept. of Comput. Sci., Oregon State Univ., Corvallis, OR, USA
pp. 1

Revisiting the Decomposition of Karp, Miller and Winograd (Abstract)

Alain Darte , Ecole Normale Sup_rieure de Lyon
Fredric Vivien , Ecole Normale Sup_rieure de Lyon
pp. 13

A Processor-Time-Minimal Schedule for 3D Rectilinear Mesh Algorithms (Abstract)

Peter Cappello , University of California Santa Barbara
Chris Scheiman , University of California Santa Barbara
pp. 26

Data Alignments for Modular Time-Space Mappings of BLAS-like Algorithms (Abstract)

Jose A.B. Fortes , Purdue University, W. Lafayette, IN 47907
Hyuk-Jae Lee , Purdue University, W. Lafayette, IN 47907
pp. 34
Session 2: Architectures I, Chair: C. Mongenet

Time-optimal ranking algorithms on sorted matrices (Abstract)

H. Gurla , Dept. of Comput. Sci., Old Dominion Univ., Norfolk, VA, USA
L. Wilson , Dept. of Comput. Sci., Old Dominion Univ., Norfolk, VA, USA
V. Bokka , Dept. of Comput. Sci., Old Dominion Univ., Norfolk, VA, USA
J.L. Schwing , Dept. of Comput. Sci., Old Dominion Univ., Norfolk, VA, USA
S. Olariu , Dept. of Comput. Sci., Old Dominion Univ., Norfolk, VA, USA
pp. 42

Recomputing by Operand Exchanging: A Time-redundancy Approach for Fault-tolerant Neural Networks (Abstract)

Vincenzo Piuri , Politecnico di Milano
Earl E. Swartzlander Jr , The University of Texas at Austin
Yuang-Ming Hsu , The University of Texas at Austin
pp. 54

A Scalable Halftoning Coprocessor Architecture (Abstract)

Roger-David Hersch , Swiss Federal Institute of Technology
Anders Kugler , Swiss Federal Institute of Technology
pp. 76

Horizontal Microcode Compaction for Programmable Systolic Accelerators (Abstract)

Paolo Ienne , Microcomputing Laboratory & Centre MANTRA
pp. 85
Session 3: Arithmetic I, Chair: R. Owens

Column Compression Pipelined Multipliers (Abstract)

Luca Breveglieri , Politecnico di Milano
Luigi Dadda , Politecnico di Milano
Vincenzo Piuri , Politecnico di Milano
pp. 93

A Processor for Staggered Interval Arithmetic (Abstract)

Earl E. Swartzlander, Jr. , The University of Texas at Austin
Michael J. Schulte , The University of Texas at Austin
pp. 104

A simple array processor for binary prefix sums (Abstract)

S. Olariu , Dept. of Comput. Sci., State Univ. of New York, Genesco, NY, USA
Rong Lin , Dept. of Comput. Sci., State Univ. of New York, Genesco, NY, USA
pp. 113
Session 4: Poster Presentations, Chair: R. Owens

The MGAP's programming environment and the *C++ language (Abstract)

M.J. Irwin , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
R.M. Owens , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
R.S. Bajwa , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
pp. 121

The VLSI design and implementation of the array processors of a multilayer vision system architecture (Abstract)

J.S. Mertoguno , Dept. of Electr. Eng., Binghamton Univ., NY, USA
N.G. Bourbakis , Dept. of Electr. Eng., Binghamton Univ., NY, USA
B. Saha , Dept. of Electr. Eng., Binghamton Univ., NY, USA
pp. 125

A Parallelizing Compilation Method for the Map-oriented Machine (Abstract)

Helmut Reinig , University of Kaiserslautern
Rainer Kress , University of Kaiserslautern
Reiner W. Hartenstein , University of Kaiserslautern
Karin Schmidt , University of Kaiserslautern
Jrgen Becker , University of Kaiserslautern
pp. 129

VLSI Algorithms for Compressed Pattern Search Using Tree Based Codes (Abstract)

Tinku Acharya , University of Maryland
Amar Mukherjee , University of Central Florida
pp. 133

Parallel Sequence Comparison and Alignment (Abstract)

Richard Hughey , University of California, Santa Cruz (UCSC)
pp. 137

The Systolic Design of a Block Regularised Parameter Estimator using Hierarchical Signal Flow Graphs (Abstract)

D.W. Brown , The Queen's University of Belfast
F.M.F. Gaston , The Queen's University of Belfast
pp. 141
Invited Talk, Chair: S.Y. Kung
Session 5: Signal and Image Processing, Chair: S. Y. Kung

A Solid Translation Engine using Ray Representation (Abstract)

Thomas Alexander , Duke University
Gershon Kedem , Duke University
John L. Ellis , Duke University
pp. 157

Synthesis of VLSI Architectures for Two-Dimensional Discrete Wavelet Transforms (Abstract)

Viktor K. Prasanna , University of Southern California
Jongwoo Bae , University of Southern California
pp. 174
Session 6: Motion Estimation, Chair: P. Quinton

Parallel Implementation of the Full Search Block Matching Algorithm for Motion Estimation (Abstract)

P. Baglietto , DIST - University of Genoa
A. Migliaro , DIST - University of Genoa
M. Migliardi , DIST - University of Genoa
M. Maresca , DIST - University of Genoa
pp. 182

MOVIE: A Building Block for the Design of Real Time Simulator of Moving Pictures Compression Algorithms (Abstract)

Francois Charot , IRISA,Campus de Beaulieu
Ronan Barzic , CCETT
Gwendal Le Fol , IRISA,Campus de Beaulieu
Charles Wagner , IRISA,Campus de Beaulieu
Pascal Lemonnier , IRISA,Campus de Beaulieu
pp. 193

Motion Estimation Algorithms on Fine Grain Array Processor (Abstract)

Mary Jane Irwin , The Pennsylvania State University
Robert Michael Owens , The Pennsylvania State University
Heung-Nam Kim , The Pennsylvania State University
pp. 204

Bit Level Block Matching Systolic Arrays (Abstract)

Yin Chan , Princeton University
S. Y. Kung , Princeton University
pp. 214
Invited Talk, Chair: J.M. Muller
Session 7: Architecture II, Chair: J.M. Muller

Techniques for Yield Enhancement of VLSI Adders (Abstract)

Israel Koren , University of Massachusetts
Zhan Chen , University of Massachusetts
pp. 222

Interfacing FPGA/VLSI Processor Arrays (Abstract)

Joseph Fernando , Wright State University
Jack Jean , Wright State University
pp. 230

Implementation of Parallel Arithmetic in a Cellular Automaton (Abstract)

Ken Steiglitz , Princeton University
Richard Squier , Georgetown University
Mariusz Jakubowski , Princeton University
pp. 238
Session 8: Arithmetic II, Chair: E.E. Swartzlander

Digit On-line Large Radix CORDIC Rotator (Abstract)

Elisardo Antelo , University of Santiago de Compostela
Emilio L. Zapata , University of Malaga
Javier D. Bruguera , University of Santiago de Compostela
Julio Villalba , University of Malaga
Javier D. Bruguera , University of Santiago de Compostela
Roberto R. Osorio , University of Santiago de Compostela
pp. 246

CORDIC Architectures with Parallel Compensation of the Scale Factor (Abstract)

E. Antelo , University of Santiago de Compostela, SPAIN
J.A. Hidalgo , University of Malaga, SPAIN
E.L. Zapata , University of Malaga, SPAIN
J.D. Bruguera , University of Santiago de Compostela, SPAIN
J. Villalba , University of Malaga, SPAIN
pp. 258

An array processor for inner product computations using a Fermat number ALU (Abstract)

G.A. Jullien , VLSI Res. Group, Windsor Univ., Ont., Canada
Z. Wang , VLSI Res. Group, Windsor Univ., Ont., Canada
W.C. Miller , VLSI Res. Group, Windsor Univ., Ont., Canada
N.M. Wigley , VLSI Res. Group, Windsor Univ., Ont., Canada
W. Luo , VLSI Res. Group, Windsor Univ., Ont., Canada
pp. 270

Multilayer Cellular Algorithm for Complex Number Multiplication (Abstract)

V.P. Markova , Computing Center, Siberian Div. of the Russian Academy of Sciences
pp. 290
Session 9: Design Methodologies, Chair: J. Fortes

Minimizing Synchronization Overhead in Statically Scheduled Multiprocessor Systems (Abstract)

Sundararajan Sriram , University of California, Berkeley California, 94720
Shuvra S. Bhattacharyya , Hitachi America Ltd.
Edward A. Lee , University of California, Berkeley California, 94720
pp. 298

Precise Tiling for Uniform Loop Nests (Abstract)

Tanguy Risset , IRISA, Campus de Beaulieu
Pierre-Yves Calland , Ecole Nationale Superieure de Lyon
pp. 330
Closing Session and Best Paper Award, Chair: J. Fortes

Index of Authors (PDF)

pp. 339
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