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Proceedings The International Conference on Application Specific Array Processors (1995)
Strasbourg, France
July 24, 1995 to July 26, 1995
ISSN: 1063-6862
ISBN: 0-8186-7109-2
pp: 93
Luca Breveglieri , Politecnico di Milano
Luigi Dadda , Politecnico di Milano
Vincenzo Piuri , Politecnico di Milano
ABSTRACT
The paper presents a study on the introduction of pipelining in parallel VLSI multipliers, built according to the column compression (CC) design techniques. A number of CC multiplier schemes have been proposed in the literature, aimed at reducing the number of stages of adders necessary to compute a multiplication. More recently CC multiplier schemes aimed at optimising the required silicon area, the regularity and the locality of the interconnections among the adders, have been proposed. The paper affords the introduction of pipelining in these last structures and compares the obtained results with existing structures, in terms of required number of components and operation frequency.
INDEX TERMS
pipelining, multipliers, computer arithmetic
CITATION

L. Breveglieri, L. Dadda and V. Piuri, "Column Compression Pipelined Multipliers," Proceedings The International Conference on Application Specific Array Processors(ASAP), Strasbourg, France, 1995, pp. 93.
doi:10.1109/ASAP.1995.522909
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