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Atlanta, Georgia
Mar. 21, 1999 to Mar. 24, 1999
ISBN: 0-7695-0056-0
pp: 256
Dana S. Henry , Yale University
Bradley C. Kuszmaul , Yale University
Vinod Viswanath , Yale University
ABSTRACT
The poor scalability of existing superscalar processors has been of great concern to the computer engineering community. In particular, the critical-path lengths of many components in existing implementations grow as T(n2) where n is the fetch width, the issue width, or the window size. This paper presents a novel implementation, called the Ultrascalar processor, that dramatically reduces the asymptotic critical-path length of a superscalar processor. The processor is implemented by a large collection of ALUs with controllers (together called execution stations) connected together by a network of parallel-prefix tree circuits. A fat-tree network connects an interleaved cache to the execution stations.
CITATION
Dana S. Henry, Bradley C. Kuszmaul, Vinod Viswanath, "The Ultrascalar Processor-An Asymptotically Scalable Superscalar Microarchitecture", ARVLSI, 1999, Advanced Research in VLSI, Conference on, Advanced Research in VLSI, Conference on 1999, pp. 256, doi:10.1109/ARVLSI.1999.756053
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