The Community for Technology Leaders
Advanced Research in VLSI, Conference on (1997)
Ann Arbor, MI
Sept. 15, 1997 to Sept. 16, 1997
ISBN: 0-8186-7913-1
TABLE OF CONTENTS

Foreword (PDF)

pp. viii

Acknowledgment (PDF)

pp. ix

Committees (PDF)

pp. x
Session 1: High-Performance Systems, Chair: Rob Rutenbar

Scalability in computing for today and tomorrow (Abstract)

David Parry , Silicon Graphics Comput. Syst., Mountain View, CA, USA
pp. 12
Session 2: Clocking and Timing, Chair: Alexander Ishii

Signal Delay in Coupled, Distributed RC Lines in the Presence of Temporal Proximity (Abstract)

V. Chandramouli , University of Michigan
Ayman I. Kayssi , American University of Beirut
Karem A. Sakallah , University of Michigan
pp. 32

Interfacing Synchronous and Asynchronous Modules Within a High-Speed Pipeline (Abstract)

Chris J. Myers , Electrical Engineering Department, University of Utah
Allen E. Sjogren , Electrical Engineering Department, University of Utah
pp. 47

Clock Distribution Using Cooperative Ring Oscillators (Abstract)

Mark Clements , North Carolina State University
Griff Bilbro , North Carolina State University
Wentai Liu , North Carolina State University
Les Hall , North Carolina State University
pp. 62
Session 3: Advanced Process and Packaging Technologies, Chair: Steve Sugiyama

Design Implementation of Intrinsic Area Array ICs (Abstract)

Peyman Dehkordi , The University of Tennessee, Knoxville
Donald Bouldin , The University of Tennessee, Knoxville
Chandra Tan , The University of Tennessee, Knoxville
pp. 82
Session 4: VLSI Systems, Chair: Mike Upton

Compact Signed-Digit Adder Using Multiple-Valued Logic (Abstract)

Alejandro F. Gonzalez , The University of Michigan
Pinaki Mazumder , The University of Michigan
pp. 96

Image Edge Enhancement, Dynamic Compression and Noise Suppression using Analog Circuit Processing (Abstract)

Todd Hinck , VLSI and Neural Net Systems Laboratory, Boston University, College of Engineering
Allyn E. Hubbard , VLSI and Neural Net Systems Laboratory, Boston University, College of Engineering
pp. 114

Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control (Abstract)

Panagiota Vatsolaki , Institute of Computer Science (ICS), Foundation for Research and Technology Hellas (FORTH)
Manolis Katevenis , Institute of Computer Science (ICS), Foundation for Research and Technology Hellas (FORTH)
Christoforos Kozyrakis , Institute of Computer Science (ICS), Foundation for Research and Technology Hellas (FORTH)
George Kornaros , Institute of Computer Science (ICS), Foundation for Research and Technology Hellas (FORTH)
pp. 127

Kestrel: Design of an 8-bit SIMD Parallel Processor (Abstract)

David M. Dahle , University of California, Santa Cruz
Hansjoerg Keller , University of California, Santa Cruz
Kevin Karplus , University of California, Santa Cruz
Don Speck , University of California, Santa Cruz
Richard Hughey , University of California, Santa Cruz
Douglas H. Williams , University of California, Santa Cruz
Jeffrey D. Hirschberg , University of California, Santa Cruz
Eric Rice , University of California, Santa Cruz
pp. 145
Session
Poster Presentations and Tours
Invited Presentation

(PDF)

pp. 0
Session 5: Asynchronous Design, Chair: William Dally

The Design of an Asynchronous MIPS R3000 Microprocessor (Abstract)

Paul Penzes , Department of Computer Science, California Institute of Technology
Rajit Manohar , Department of Computer Science, California Institute of Technology
Uri Cummings , Department of Computer Science, California Institute of Technology
Mika Nystroem , Department of Computer Science, California Institute of Technology
Alain J. Martin , Department of Computer Science, California Institute of Technology
Andrew Lines , Department of Computer Science, California Institute of Technology
Robert Southworth , Department of Computer Science, California Institute of Technology
pp. 164

A VLSI Architecture for Modeling Intersegmental Coordination (Abstract)

David E. Schimmel , Georgia Institute of Technology Emory University
Girish N. Patel , Georgia Institute of Technology Emory University
Stephen P. DeWeerth , Georgia Institute of Technology Emory University
Ronald L. Calabrese , Georgia Institute of Technology Emory University
Mario F. Simoni , Georgia Institute of Technology Emory University
pp. 182

A High-Speed Asynchronous Decompression Circuit for Embedded Processors (Abstract)

Steven M. Nowick , Columbia University
Andrew Wolfe , Princeton University
Martin Benes , University of California, Berkeley
pp. 219
Session 6: Reconfigurable Logic Circuits, Chair: Jim Aylor

Fault Scanner for Reconfigurable Logic (Abstract)

William H. Mangione-Smith , Electrical Engineering Department, University of California, Los Angeles
Nathan R. Shnidman , Electrical Engineering Department, University of California, Los Angeles
Miodrag Potkonjak , Computer Science Department, University of California, Los Angeles
pp. 238

Architectural Design of a Three Dimensional FPGA (Abstract)

Miriam Leeser , Northeastern University
Waleed M. Meleis , Northeastern University
Mankuan M. Vai , Northeastern University
Paul Zavracky , Northeastern University
pp. 256
Session 7: Radio Frequency Circuits, Chair: Bryan Ackland

Next-Generation RF Circuits and Systems (Abstract)

Behzad Razavi , Department of Electrical Engineering, University of California, Los Angeles
pp. 270
Session 8: Advanced Architectures, Chair: Randy Bryant

Circuits and Microarchitecture for Gigahertz VLSI Designs (Abstract)

Kevin J. Nowka , IBM Austin Research Laboratory
H. Peter Hofstee , IBM Austin Research Laboratory
pp. 284

An Embedded DRAM for CMOS ASICs (Abstract)

John Poulton , Department of Computer Science, University of North Carolina
pp. 288

The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors (Abstract)

Lance Hammond , Stanford University
Kunle Olukotun , Stanford University
Tadaaki Yamauchi , ULSI Laboratory, Mitsubishi Electric Corporation
pp. 303

Author Index (PDF)

pp. 320
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