The Community for Technology Leaders
Advanced Research in VLSI, Conference on (1995)
Chapel Hill, North Carolina
Mar. 27, 1995 to Mar. 29, 1995
ISBN: 0-8186-7047-9
TABLE OF CONTENTS

Foreward (PDF)

pp. ix

Committees (PDF)

pp. x
Invited Presentation
Session I: VLSI Architecture, Chair: John Poulton

Combined DRAM and logic chip for massively parallel systems (Abstract)

H. Miyataka , Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
P.M. Kogge , Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
K. Kitamura , Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
T. Sunaga , Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
E. Retter , Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
pp. 4

Silicon VLSI processing architectures incorporating integrated optoelectronic devices (Abstract)

M. Brooke , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
N.M. Jokerst , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
B. Buchanan , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
M. Lee , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
D.S. Wills , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
H.H. Cat , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 17
Session II: Asynchronous Design, Chair: Scott Wills

Automatic synthesis of gate-level timed circuits with choice (Abstract)

C.J. Myers , Stanford Univ., CA, USA
T.G. Rokicki , Stanford Univ., CA, USA
T.H.-Y. Meng , Stanford Univ., CA, USA
pp. 42

Algorithms for the optimal state assignment of asynchronous state machines (Abstract)

R.M. Fuhrer , Dept. of Comput. Sci., Columbia Univ., New York, NY, USA
B. Lin , Dept. of Comput. Sci., Columbia Univ., New York, NY, USA
S.M. Nowick , Dept. of Comput. Sci., Columbia Univ., New York, NY, USA
pp. 59

Low latency self-timed flow-through FIFOs (Abstract)

E. Brunvand , Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA
pp. 76

High speed counterflow-clocked pipelining illustrated on the design of HDTV subband vector quantizer chips (Abstract)

K.F. Smith , Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA
Jae-Tack Yoo , Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA
G. Gopalakrishnan , Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA
V.J. Mathews , Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA
pp. 91
Session III: Circuits, Chair: Tom Knight

Bit-serial bidirectional A/D/A conversio (Abstract)

G. Cauwenberghs , Dept. of Electr. & Comput. Eng., Johns Hopkins Univ., Baltimore, MD, USA
pp. 108

Dynamic CMOS circuit techniques for delay and power reduction in parallel adders (Abstract)

P. Andersson , Dept. of Comput. Eng., Lund Univ., Sweden
H. Lindkvist , Dept. of Comput. Eng., Lund Univ., Sweden
pp. 121

A technique for high-speed, fine-resolution pattern generation and its CMOS implementation (Abstract)

G.C. Moyer , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
Wentai Liu , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
T. Schaffer , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
R.K. Cavin, III , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
M. Clements , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
pp. 131
Invited Presentation
Session lV: Miscellaneous, Chair: Alain Martin

Array-of-arrays architecture for parallel floating point multiplication (Abstract)

M. Horowitz , Center for Integrated Syst., Stanford Univ., CA, US
H. Dhanesha , Center for Integrated Syst., Stanford Univ., CA, US
K. Falakshahi , Center for Integrated Syst., Stanford Univ., CA, US
pp. 150

A multi-sender asynchronous extension to the AER protocol (Abstract)

J. Lazzaro , Comput. Sci. Div., California Univ., Berkeley, CA, USA
J. Wawrzynek , Comput. Sci. Div., California Univ., Berkeley, CA, USA
pp. 158
Session V: Layout, Chair: Neil Weste

Recursive layout generation (Abstract)

R.W. Haddad , Western Res. Lab., Digital Equipment Corp., Palo Alto, CA, USA
J. Dion , Western Res. Lab., Digital Equipment Corp., Palo Alto, CA, USA
L.M. Monier , Western Res. Lab., Digital Equipment Corp., Palo Alto, CA, USA
pp. 172

HAL: heuristic algorithms for layout synthesis (Abstract)

J.D. Trotter , Mississippi State Univ., MS, USA
S. Rekhi , Mississippi State Univ., MS, USA
pp. 185

Efficient Galerkin techniques for multipole-accelerated capacitance extraction of 3-D structures with multiple dielectrics (Abstract)

K. Nabors , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
X. Cai , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
J. White , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
pp. 200
Session VI: Image Sensors, Chair: Bryan Ackland

Standard CMOS active pixel image sensors for multimedia applications (Abstract)

E.-S. Eid , AT&T Bell Labs., Holmdel, NJ, USA
B. Ackland , AT&T Bell Labs., Holmdel, NJ, USA
E.R. Fossum , AT&T Bell Labs., Holmdel, NJ, USA
D. Inglis , AT&T Bell Labs., Holmdel, NJ, USA
A. Dickinson , AT&T Bell Labs., Holmdel, NJ, USA
pp. 214

A 590,000 transistor 48,000 pixel, contrast sensitive, edge enhancing, CMOS imager-silicon retina (Abstract)

A.G. Andreou , Dept. of Electr. & Comput. Eng., Johns Hopkins Univ., Baltimore, MD, USA
K.A. Boahen , Dept. of Electr. & Comput. Eng., Johns Hopkins Univ., Baltimore, MD, USA
pp. 225

Analog VLSI circuits for manufacturing inspection (Abstract)

D.M. Wilson , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
T.G. Morris , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
P. DeWeerth , Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 241
Session VII: Optimization, Chair: Kurt Keutzer

OPTIMUS: a new program for OPTIMizing linear circuits with number-splitting and shift-and-add decompositions (Abstract)

Huy Nguyen , Sch. of Electr. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
A. Chatterjee , Sch. of Electr. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 258

Code density optimization for embedded DSP processors using data compression techniques (Abstract)

S.Y. Liao , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
S. Devadas , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
K. Keutzer , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
pp. 272

Systematic objective-driven computer architecture optimization (Abstract)

T.J. Stanley , Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA
T. Mudge , Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA
pp. 286
Invited Presentation
Session VIII: System Timing, Chair: Alex Ishii

Low-latency plesiochronous data retiming (Abstract)

D. Xanthopoulos , Artificial Intelligence Lab., MIT, Cambridge, MA, USA
W.J. Dally , Artificial Intelligence Lab., MIT, Cambridge, MA, USA
L.R. Dennison , Artificial Intelligence Lab., MIT, Cambridge, MA, USA
pp. 304

Distributed synchronous clocking (Abstract)

G.A. Pratt , Comput. Sci. Lab., MIT, Cambridge, MA, USA
J. Nguyen , Comput. Sci. Lab., MIT, Cambridge, MA, USA
pp. 316

Single-transistor transparent-latch clocking (Abstract)

Kei-Yong Khoo , Integrated Circuits & Syst. Lab., California Univ., Los Angeles, CA, USA
A.N. Willson, Jr. , Integrated Circuits & Syst. Lab., California Univ., Los Angeles, CA, USA
pp. 331

On the performance of level-clocked circuits (Abstract)

B. Lockyear , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
C. Ebeling , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
pp. 342
Session IX: CAD, Chair: Srinivas Devadas

Quasi-algebraic decompositions of switching functions (Abstract)

T. Stanion , Dept. of Electr. Eng., Washington Univ., USA
C. Sechen , Dept. of Electr. Eng., Washington Univ., USA
pp. 358

Efficient retiming under a general delay model (Abstract)

K.N. Lalgudi , Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA
M.C. Papaefthymiou , Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA
pp. 368

An evaluation of bipartitioning techniques (Abstract)

S. Hauck , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
G. Borriello , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
pp. 383
Session X: Low-Power Design, Chair: Rich Brown

Non-dissipative rail drivers for adiabatic circuits (Abstract)

T.F. Knight, Jr. , Artificial Intelligence Lab., MIT, Cambridge, MA, USA
S.G. Younis , Artificial Intelligence Lab., MIT, Cambridge, MA, USA
pp. 404

Energy recovery for low-power CMOS (Abstract)

N. Tzartzanis , Inf. Sci. Inst., Univ. of Southern California, Marina del Rey, CA, USA
W.C. Athas , Inf. Sci. Inst., Univ. of Southern California, Marina del Rey, CA, USA
pp. 415

Optimization of combinational and sequential logic circuits for low power using precomputation (Abstract)

A. Ghosh , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
S. Devadas , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
J. Rinderknecht , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
J. Monteiro , Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
pp. 430
Invited Presentation

Author Index (PDF)

pp. 447
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