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Proceedings. International Conference on Systolic Arrays (1988)
San Diego, CA, USA
May 25, 1988 to May 27, 1988
ISBN: 0-8186-8860-2
TABLE OF CONTENTS

Systolic array for 2-D adaptive beamforming (PDF)

T.V. Vo , McMaster Univ., Hamilton, Ont., Canada
J. Litva , McMaster Univ., Hamilton, Ont., Canada
pp. 1-10

An efficient systolic array for MVDR beamforming (PDF)

J.G. McWhirter , R. Signals & Radar Establ., Malvern, UK
T.J. Shepherd , R. Signals & Radar Establ., Malvern, UK
pp. 11-20

Implementation of synthetic aperture radar algorithms on a systolic/cellular architecture (PDF)

K.W. Przytula , Hughes Res. Lab., Malibu, CA, USA
J.G. Nash , Hughes Res. Lab., Malibu, CA, USA
pp. 21-30

Architecture of a programmable systolic array (PDF)

R. Hughey , Dept. of Comput. Sci., Brown Univ., Providence, RI, USA
D.P. Lopresti , Dept. of Comput. Sci., Brown Univ., Providence, RI, USA
pp. 41-49

Synthesizing optimal family of linear systolic arrays for matrix computations (PDF)

V.K.P. Kumar , Univ. of Southern California, Los Angeles, CA, USA
Y.-C. Tsai , Univ. of Southern California, Los Angeles, CA, USA
pp. 51-60

Theory for systolizing global computational problems (PDF)

W. Liu , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
pp. 61-71

New architectures for systolic hashing (PDF)

G. Panneerselvam , VLSI Res. Group, Windsor Univ., Ont., Canada
G.A. Jullien , VLSI Res. Group, Windsor Univ., Ont., Canada
W.C. Miller , VLSI Res. Group, Windsor Univ., Ont., Canada
pp. 73-82

Linear systolic array for least-squares estimation (PDF)

M.-J. Chen , Tektronix Inc., Beaverton, OR, USA
pp. 83-92

A cellular algorithm for straight line extraction (PDF)

T. De Saint Pierre , Lab. de Robotique de Paris, Univ. Pierre et Marie Curie, Paris, France
M. Milgram , Lab. de Robotique de Paris, Univ. Pierre et Marie Curie, Paris, France
pp. 93-102

A one dimensional systolic array for solving arbitrarily large least mean square problems (PDF)

N. Torralba , Dept. Arquitectura Computadors, Univ. Politecnica Catalunya, Barcelona, Spain
J.J. Navarro , Dept. Arquitectura Computadors, Univ. Politecnica Catalunya, Barcelona, Spain
pp. 103-112

Performance evaluation of the HERMES multibit systolic array architecture for low level processing tasks (PDF)

N. Bourbakis , Dept. of Electr. & Comput. Eng., George Mason Univ., Fairfax, VA, USA
F. Barlos , Dept. of Electr. & Comput. Eng., George Mason Univ., Fairfax, VA, USA
pp. 113-124

On partitioning the Faddeev algorithm (PDF)

J.H. Moreno , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
T. Lang , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 125-134

A systolic architecture for the symmetric tridiagonal eigenvalue problem (PDF)

W. Phillips , Dept. of Appl. Math., Tech. Univ. of Nova Scotia, Halifax, NS, Canada
W. Robertson , Dept. of Appl. Math., Tech. Univ. of Nova Scotia, Halifax, NS, Canada
pp. 145-150

Systolic FFT algorithms on Boolean cube networks (PDF)

L. Johnson , Thinking Machines Corp., Cambridge, MA, USA
pp. 151-162

Parallel architectures for artificial neural nets (PDF)

S.Y. King , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 163-174

Stereo matching of satellite images with transputers (PDF)

K.A. Collins , Thorn EMI Central Res. Lab., Hayes, UK
pp. 175-182

The use of linear arrays for image processing (PDF)

T.J. Fountain , Dept. of Phys. & Astron., Univ. Coll. London, UK
pp. 183-192

A million transistor systolic array graphics engine (PDF)

N. Gharachorloo , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
S. Gupta , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
E. Hokenek , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
P. Balasubramanian , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
W. Bogholtz , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
C. Mathieu , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
C. Zoulas , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 193-202

A systolic array with constant I/O bandwidth for the generalized Fourier transform (PDF)

H. Hellwagner , Syst. Theory & Inf. Eng., Linz Univ., Austria
pp. 207-216

A massively parallel systolic array processor system (PDF)

R.E. Morley , Washington Univ., St. Louis, MO, USA
T.J. Sullivan , Washington Univ., St. Louis, MO, USA
pp. 217-225

Implementation of array structured maximum likelihood decoders (PDF)

K.-A. Wen , Inst. of Electr. & Comput. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
J.-F. Wang , Inst. of Electr. & Comput. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
J.-Y. Lee , Inst. of Electr. & Comput. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
M.-Y. Lin , Inst. of Electr. & Comput. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
pp. 227-236

Regular processor arrays for matrix algorithms with pivoting (PDF)

V.P. Roychowdhury , Inf. Syst. Lab., Stanford Univ., CA, USA
T. Kailath , Inf. Syst. Lab., Stanford Univ., CA, USA
pp. 237-246

Systolic algorithms for some scheduling and graph problems (Abstract)

O.H. Ibarra , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
T. Jiang , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
pp. 247-256

A shortperiodic two-dimensional systolic sorting algorithm (PDF)

U. Schwiegelshohn , Inst. of Network Theory & Circuit Design, Tech. Univ. Munich, West Germany
pp. 257-264

A block algorithm for the algebraic path problem and its execution on a systolic array (PDF)

F.J. Nunez , Dept. de Arquitectura de Computadores, Univ. Politecnica de Cataluna, Barcelona, Spain
M. Valero , Dept. de Arquitectura de Computadores, Univ. Politecnica de Cataluna, Barcelona, Spain
pp. 265-274

The design of a systolic array system for linear state equations (PDF)

S.-J. Jou , Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan
C.-W. Jen , Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan
W.-Z. Shen , Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 275-284

Mapping strategy for automatic design of systolic arrays (PDF)

C.K. Ko , Dept. of Electr. Eng., Columbia Univ., New York, NY, USA
O. Wing , Dept. of Electr. Eng., Columbia Univ., New York, NY, USA
pp. 285-294

Transitive closure on an instruction systolic array (PDF)

H.-W. Lang , Inst. fuer Inf. & Praktische Math., Christian-Albrechts-Univ. Kiel, West Germany
pp. 295-304

The derivation of regular synchronous circuits (PDF)

W. Luk , Comput. Lab., Oxford Univ., UK
G. Jones , Comput. Lab., Oxford Univ., UK
pp. 305-314

Systolic arrays for group explicit methods for solving parabolic partial differential equations (PDF)

D.J. Evans , Dept. of Comput. Studies, Loughborough Univ. of Technol., UK
G.M. Megson , Dept. of Comput. Studies, Loughborough Univ. of Technol., UK
pp. 315-329

Formal derivation of systolic arrays-a case study (PDF)

M. Payer , Inst. fuer Inf., Tech. Univ. Munchen, West Germany
pp. 331-340

Parallel algorithms and systolic array designs for RSA cryptosystem (PDF)

C.N. Zhang , Dept. of Electr. Eng., North Carolina A&T State Univ., Greensboro, NC, USA
H.L. Martin , Dept. of Electr. Eng., North Carolina A&T State Univ., Greensboro, NC, USA
pp. 341-350

Mapping systolic algorithms into shuffle arrays (PDF)

W.-T. Lin , Gen. Electr. Co., Schenectady, NY, USA
pp. 351-360

A systolic algorithm and architecture for solving sets of linear equations with multi-band coefficient matrix (PDF)

P.F.C. Krekel , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
E.F. Deprettere , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 361-371

Scheduling a system of affine recurrence equations onto a systolic array (PDF)

Y. Yaacoby , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 373-382

SYSTARS: A CAD tool for the synthesis and analysis of VLSI systolic/wavefront arrays (PDF)

E.T.L. Omtzigt , Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA
pp. 383-391

Time optimal linear schedules for algorithms with uniform dependencies (PDF)

W. Shang , Sch. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
J.A.B. Fortes , Sch. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 393-402

Broadcast removal in systolic algorithms (PDF)

Y. Wong , Yale Univ., New Haven, CT, USA
J.-M. Delosme , Yale Univ., New Haven, CT, USA
pp. 403-412

HIFI: a functional design system for VLSI processing arrays (PDF)

J. Annevelink , Delft Univ. of Technol., Netherlands
P. Dewilde , Delft Univ. of Technol., Netherlands
pp. 413-452

A pragmatic approach to systolic design (PDF)

S. Manohar , Dept. of Comput. Sci., Brown Univ., Providence, RI, USA
pp. 463-472

A linear algebraic model of algorithmic-based fault tolerance (PDF)

C.J. Anfinson , Center for Appl. Math., Cornell Univ., Ithaca, NY, USA
pp. 483-493

New conditions for testability of two-dimensional bilateral arrays (PDF)

D. Sciuto , Dept. of Electron., Politecnico di Milano, Italy
pp. 495-504

On the design of easily testable and reconfigurable systolic arrays (PDF)

J.H. Kim , Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
pp. 505-514

The ASP, a fault tolerant VLSI/ULSI/WSI associative string processor for cost-effective systolic processing (PDF)

R.M. Lea , Dept. of Electr. Eng. & Electron., Brunel Univ., Uxbridge, UK
pp. 515-524

Cellular array processor CAP and applications (PDF)

M. Ishi , Fujitsu Lab. Ltd., Kawasaki, Japan
H. Sato , Fujitsu Lab. Ltd., Kawasaki, Japan
K. Murakami , Fujitsu Lab. Ltd., Kawasaki, Japan
M. Ikesaka , Fujitsu Lab. Ltd., Kawasaki, Japan
H. Ishihata , Fujitsu Lab. Ltd., Kawasaki, Japan
pp. 535-544

A probabilistic model for clock skew (PDF)

S.D. Kugelmass , Dept. of Comput. Sci., Princeton Univ., NJ, USA
K. Steiglitz , Dept. of Comput. Sci., Princeton Univ., NJ, USA
pp. 545-554

Interconnection complexity study for a piggy back WSHP GaAs systolic processor (PDF)

R. Philhower , Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA
J.F. McDonald , Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA
pp. 555-564

Policies for fault-tolerance through mixed space- and time-redundancy in semi-systolic FFT arrays (PDF)

A. Antola , Dept. of Electron., Politecnico di Melano, Italy
R. Negrini , Dept. of Electron., Politecnico di Melano, Italy
M.G. Sami , Dept. of Electron., Politecnico di Melano, Italy
N. Scarabottolo , Dept. of Electron., Politecnico di Melano, Italy
pp. 565-576

A systolic integrated circuit integer divider (PDF)

J.A. Eldon , TRW LSI Products, La Jolla, CA, USA
pp. 587-591

An efficient asynchronous multiplier (PDF)

R.M. Goodman , Dept. of Electr. Eng., California Inst. of Technol., Pasadena, CA, USA
pp. 593-599

Homogeneous multicomputer type DSP system NOVI for parallel signal processing (PDF)

N. Ohta , Transmission Syst. Lab., NTT, Yokosuka, Japan
T. Fujii , Transmission Syst. Lab., NTT, Yokosuka, Japan
Y. Kanayama , Transmission Syst. Lab., NTT, Yokosuka, Japan
S. Ono , Transmission Syst. Lab., NTT, Yokosuka, Japan
pp. 601-610

A multiprocessor system utilizing enhanced DSPs for image processing (PDF)

H. Ueda , Hitachi Ltd., Tokyo, Japan
K. Kato , Hitachi Ltd., Tokyo, Japan
H. Matsushima , Hitachi Ltd., Tokyo, Japan
K. Kaneko , Hitachi Ltd., Tokyo, Japan
M. Ejiri , Hitachi Ltd., Tokyo, Japan
pp. 611-620

Architecture of SIPS, a real time image processing system (PDF)

A. Hasebe , Sony Corp., Kanagawa, Japan
J. Yonemitsu , Sony Corp., Kanagawa, Japan
R. Kato , Sony Corp., Kanagawa, Japan
N. Ito , Sony Corp., Kanagawa, Japan
H. Fujita , Sony Corp., Kanagawa, Japan
pp. 621-630

A reconfigurable VLSI array for reliability and yield enhancement (PDF)

S.P. Popli , Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, IN, USA
M.A. Bayoumi , Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, IN, USA
pp. 631-642

A systolic square root information Kalman filter (PDF)

F.M.F. Gaston , Dept. of Electr. & Electron. Eng., Queen's Univ. of Belfast, UK
G.W. Irwin , Dept. of Electr. & Electron. Eng., Queen's Univ. of Belfast, UK
pp. 643-652

Bit-level systolic arrays for IIR filtering (PDF)

S.C. Knowles , R. Signals & Radar Establ., Malvern, UK
pp. 653-663

A high level synthesis tool for systolic designs (PDF)

P.-P. Hou , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
R.M. Owens , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
M.J. Irwin , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
pp. 665-673

Systolic array system for vector quantization using transformed sub-band coding (PDF)

M. Yan , Dept. of Electr. & Electron. Eng., Queen's Univ. of Belfast, UK
J.V. McCanny , Dept. of Electr. & Electron. Eng., Queen's Univ. of Belfast, UK
H.A. Kaouri , Dept. of Electr. & Electron. Eng., Queen's Univ. of Belfast, UK
pp. 675-684

A systematic approach to bit recursive systolic array design (PDF)

K.R. Liu , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
K. Yao , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
pp. 685-694

Systolic communication (PDF)

H.T. Kung , Dept. of Comput. Sci., Carnegie-Mellon Univ., Pittsburgh, PA, USA
pp. 695-703
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