June 25, 2007 to June 27, 2007
Mark A. Erle , International Business Machines
Michael J. Schulte , University of Wisconsin, Madison
Brian J. Hickmann , University of Wisconsin, Madison
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ARITH.2007.14
Decimal multiplication is important in many commercial applications including financial analysis, banking, tax calculation, currency conversion, insurance, and accounting. This paper presents the design of a decimal floating-point multiplier that complies with specifications for decimal multiplication given in the draft revision of the IEEE 754 Standard for Floating-point Arithmetic (IEEE 754R). This multiplier extends a previously published decimal fixedpoint multiplier design by adding several features including exponent generation, sticky bit generation, shifting of the intermediate product, rounding, and exception detection and handling. The core of the decimal multiplication algorithm is an iterative scheme of partial product accumulation employing decimal carry-save addition to reduce the critical path delay. Novel features of the proposed multiplier include support for decimal floating-point numbers, on-thefly generation of the sticky bit, early estimation of the shift amount, and efficient decimal rounding. Area and delay estimates are provided for a verified Verilog register transfer level model of the multiplier.
Mark A. Erle, Michael J. Schulte, Brian J. Hickmann, "Decimal Floating-Point Multiplication Via Carry-Save Addition", ARITH, 2007, Computer Arithmetic, IEEE Symposium on, Computer Arithmetic, IEEE Symposium on 2007, pp. 46-55, doi:10.1109/ARITH.2007.14