Computer Arithmetic, IEEE Symposium on (2003)

Santiago de Compostela, Spain

June 15, 2003 to June 18, 2003

ISSN: 1063-6889

ISBN: 0-7695-1894-X

pp: 245

Sorin Cotofana , Delft University of Technology

Casper Lageweg , Delft University of Technology

Stamatis Vassiliadis , Delft University of Technology

ABSTRACT

In this paper we investigate the implementation of basic arithmetic functions, such as addition and multiplication, in Single Electron Tunneling (SET) technology. First, we describe the SET equivalents of Boolean CMOS gates and Threshold logic gates. Second, we propose a set of building blocks, which can be utilized for a novel design style, namely arithmetic operations performed by direct manipulation of the location of individual electrons within the system. Using this new set of building blocks, we propose several novel approaches for computing addition related arithmetic operations via the controlled transport of charge (individual electrons). In particular, we prove the following: n-bit addition can be implemented with a depth-2 network built with 0(n) circuit elements; n-input parity can be computed with a depth-2 network constructed with 0(n) circuit elements and the same applies for n|logn counters; multiple operand addition of m n-bit operands can be implemented with a depth-2 network using 0(mn) circuit elements; and finally n-bit multiplication can be implemented with a depth-3 network built with 0(n) circuit elements.

INDEX TERMS

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CITATION

S. Cotofana, C. Lageweg and S. Vassiliadis, "On Computing Addition Related Arithmetic Operations via Controlled Transport of Charge,"

*Computer Arithmetic, IEEE Symposium on(ARITH)*, Santiago de Compostela, Spain, 2003, pp. 245.

doi:10.1109/ARITH.2003.1207685

CITATIONS