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Computer Arithmetic, IEEE Symposium on (2001)
Vail, Colorado
June 11, 2001 to June 13, 2001
ISBN: 0-7695-1150-3

Foreword (PDF)

pp. ix

Committees (PDF)

pp. x
Keynote Speech
Session 1: Binary Strings in Computer Arithmetic

Leading Zero Anticipation and Detection?A Comparison of Methods (Abstract)

Martin S. Schmookler , IBM Server Development
Kevin J. Nowka , IBM Austin Research Laboratory
pp. 0007

Bounds on Runs of Zeros and Ones for Algebraic Functions (Abstract)

Tomas Lang , University of California at Irvine
Jean-Michel Muller , Ecole Normale Superieure de Lyon
pp. 0013
Session 2: Multiplication and Exponentiation

Binary Multiplication Radix-32 and Radix-256 (Abstract)

David W Matula , Southern Methodist University
Peter-Michael Seidel , Southern Methodist University
Lee D McFearin , Southern Methodist University
pp. 0023

Analysis of Column Compression Multipliers (Abstract)

K'Andrea C. Bickerstaff , University of Texas at Austin
Michael J. Schulte , Lehigh University
Earl E. Swartzlander Jr , University of Texas at Austin
pp. 0033

Faithful Powering Computation Using Table Look-Up and a Fused Accumulation Tree (Abstract)

J.M. Muller , Ecole Normale Superieure de Lyon
J.A. Piñeiro , University Santiago de Compostela
J.D. Bruguera , University Santiago de Compostela
pp. 0040
Session 3: Cryptography

Modular Multiplication and Base Extensions in Residue Number Systems (Abstract)

Laurent-Stephane Didier , Universite de Bretagne Occidentale
Peter Kornerup , SDU/Odense University
pp. 0059
Session 4: Division and Square Root

Correctly Rounded Reciprocal Square-Root by Digit Recurrence and Radix-4 Implementation (Abstract)

Tomas Lang , University of California at Irvine
Elisardo Antelo , University of Santiago
pp. 0083

Improved Table Lookup Algorithms for Postscaled Division (Abstract)

David W. Matula , Southern Methodist University
pp. 0101
Session 5: Elementary Functions and Rounding

Worst Cases for Correct Rounding of the Elementary Functions in Double Precision (Abstract)

Jean-Michel Muller , Ecole Normale Superieure de Lyon
Vincent Lefévre , INRIA, Projet Spaces, LORIA, Campus Scientifique
pp. 0111

Generation and Analysis of Hard to Round Cases for Binary Floating Point Division (Abstract)

Lee D. McFearin , Southern Methodist University
David W. Matula , Southern Methodist University
pp. 0119

Some Improvements on Multipartite Table Methods (Abstract)

Florent de Dinechin , Ecole Normale Superieure de Lyon-INRIA
Arnaud Tisserand , Ecole Normale Superieure de Lyon-INRIA
pp. 0128

High-Performance Architectures for Elementary Function Generation (Abstract)

Belle W.Y. Wei , San Jose State University
Jun Cao , San Jose State University
Jie Cheng , San Jose State University
pp. 0136
Session 6: Number Systems

A Decimal Floating-Point Specification (Abstract)

Ronald M. Smith , IBM Server Division
Charles F. Webb , IBM Server Division
Eric M. Schwarz , IBM Server Division
pp. 0147

Algorithms for Quad-Double Precision Floating Point Arithmetic (Abstract)

David H. Bailey , NERSC: Lawrence Berkeley National Laboratory
Xiaoye S. Li , NERSC: Lawrence Berkeley National Laboratory
Yozo Hida , University of California, Berkley
pp. 0155

Effective Continued Fractions (Abstract)

David Lester , Manchester University
pp. 0163
Session 7: Floating Point Units

1-GHz HAL SPARC64? Dual Floating Point Unit with RAS Features (Abstract)

Ajay Naini , HAL Computer Systems
Warren James , HAL Computer Systems
Atul Dhablania , HAL Computer Systems
Debjit Das Sarma , HAL Computer Systems
pp. 0173

On the Design of Fast IEEE Floating-Point Adders (Abstract)

Guy Even , Tel-Aviv University
Peter-Michael Seidel , Southern Methodist University
pp. 0184

In-Order Issue Out-of-Order Execution Floating-Point Coprocessor for CalmRISC32 (Abstract)

Moon-Key Lee , Yonsei University
Tack-Don Han , Yonsei University
Woo-Chan Park , Yonsei University
Cheol-Ho Jeong , Yonsei University
Sang-Woo Kim , Samsung Electronics Co.
pp. 0195
Session 8: Addition

Using the Reverse-Carry Approach for Double Datapath Floating-Point Addition (Abstract)

Tomas Lang , University of California at Irvine
Javier D. Bruguera , University of Santiago de Compostela
pp. 0203

High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands (Abstract)

D. Nikolos , University of Patras
H.T. Vergos , University of Patras
C. Efstathiou , TEI of Athens
pp. 0211

Parallel Prefix Adder Design (Abstract)

Andrew Beaumont-Smith , The University of Adelaide
Cheng-Chew Lim , The University of Adelaide
pp. 0218
Session 9: Logarithmic Number Systems

Low-Power Properties of the Logarithmic Number System (Abstract)

T. Stouraitis , University of Patras
V. Paliouras , University of Patras
pp. 0229

The Use of the Multi-Dimensional Logarithmic Number System in DSP Applications (Abstract)

L. Imbert , University of Windsor
G. A. Jullien , University of Windsor
W.C. Miller , University of Windsor
J. Eskritt , University of Windsor
V. S. Dimitrov , University of Windsor
pp. 0247
Session 10: On-Line Arithmetic

A Design of Radix-2 On-line Division Using LSA Organization (Abstract)

Alexandre F. Tenca , Oregon State University
Syed Ubaid Hussaini , University of Applied Sciences, Offenburg, Germany
pp. 0266
Addendum: Reprinted Paper from the 14th Computer Arithmetic Symposium

A Family of Adders (Abstract)

Simon Knowles , Aztec Centre
pp. 0277
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