2008 IEEE Asia-Pacific Services Computing Conference (2008)
Dec. 9, 2008 to Dec. 12, 2008
Many videotexts exist in TV programs. Some videotexts provide valuable information. Thus, an efficient design to extract these videotexts is requested. Existing videotext extractors work on the PC platform and they are difficult to achieve real-time extraction and integration. Therefore, this work designs a videotext extractor on a dual-core platform. A distributed design framework for a dual-core platform is proposed. The extraction task is dispatched to the ARM and the DSP. The ARM core executes capture, display, control, and extraction threads. The DSP core performs algorithms. The ARM and the DSP communicate by buffers and solid channels. On the DSP side, some techniques are manipulated to optimize the videotext extractor. They include software pipeline, internal memory, adjusted program, assembly optimization, and DMA. To achieve high performance, two transferred schemes of DMA are proposed. This system is implemented on the TI Davinci DM6446 platform. All input videos are 720 x 480 with 30 fps captured from real-time DVB-T system. The simulation result shows that this extractor can process the large-size frames, and all the videotext can be extracted. With this novel architecture, the extraction speed can be enhanced to 23 frames per second.
dual-core design, videotext extraction, dsp optimization
R. Kuo, T. Tsai and C. Fang, "Design and Implementation of a Videotext Extractor on Dual-Core Platform," 2008 IEEE Asia-Pacific Services Computing Conference(APSCC), vol. 00, no. , pp. 896-900, 2008.