Conference Record of the Thirty-First Asilomar Conference on Signals, Systems and Computers (Cat. No.97CB36163) (1997)
Pacific Grove, CA, USA
Nov. 2, 1997 to Nov. 5, 1997
R. Sridhar , State Univ. of New York, Buffalo, NY, USA
Increased use of portable applications has placed severe limitations on the power consumed by processors and systems. This is particularly true for digital signal processors. Many researchers are now considering power minimization through modification of the high level software and the algorithms. This however will be more effective if a realistic power model for the instructions and the various types of memory accesses were developed. The power consumed in the fetch and the execution of any instruction is dependent on a number of factors, including the state of various functional units associated with the operation and their input patterns. This requires a careful model for the power consumption for any instruction. This paper presents a metric for such a model and its use in determining the power consumption for a given program. This is then used to rewrite the code to achieve considerable power reduction.
digital signal processing chips, power consumption, software engineering
R. Sridhar and K. Schindler, "Instruction level power model and its application to general purpose processors," Conference Record of the Thirty-First Asilomar Conference on Signals, Systems and Computers (Cat. No.97CB36163)(ACSSC), Pacific Grove, CA, USA, , pp. 753-756.