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Proceedings of 1994 28th Asilomar Conference on Signals, Systems and Computers (1994)
Pacific Grove, CA, USA
Oct. 31, 1994 to Nov. 2, 1994
ISSN: 1058-6393
ISBN: 0-8186-6405-3
pp: 1407-1411
W.S. Song , Lincoln Lab., MIT, Lexington, MA, USA
ABSTRACT
A very-high-speed radar front-end signal processing CMOS VLSI chip-set using a fully efficient bit-level systolic array architecture has been developed by MIT Lincoln Laboratory. The chip-set performs baseband quadrature sampling, channel equalization, pulse compression, and digital beamforming. The highly pipelined fully efficient bit-level systolic architecture and the highly optimized scalable CMOS VLSI cell library design give the chip-set extremely high performance. The chip-set uses an efficient 4:1 down-sampling baseband quadrature sampling architecture with reduced computational requirement. The chip-set and the cell library have potential in a variety of applications such as communications and medical imaging.<>
INDEX TERMS
very high speed integrated circuits, CMOS digital integrated circuits, systolic arrays, radar signal processing, signal sampling, pulse compression, radar computing, pipeline processing, digital signal processing chips, adaptive radar
CITATION

W. Song, "VLSI bit-level systolic array for radar front-end signal processing," Proceedings of 1994 28th Asilomar Conference on Signals, Systems and Computers(ACSSC), Pacific Grove, CA, USA, 1995, pp. 1407-1411.
doi:10.1109/ACSSC.1994.471689
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