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Proceedings of 1994 28th Asilomar Conference on Signals, Systems and Computers (1994)
Pacific Grove, CA, USA
Oct. 31, 1994 to Nov. 2, 1994
ISSN: 1058-6393
ISBN: 0-8186-6405-3
pp: 1402-1406
R. Lin , Dept. of Comput. Sci., State Univ. of New York, Geneseo, NY, USA
S. Olariu , Dept. of Comput. Sci., State Univ. of New York, Geneseo, NY, USA
ABSTRACT
In this paper we adopt and modify the shift switching mechanism to propose a novel VLSI inner product processor architecture involving broadcasting on short buses, i.e. buses with no more than 8 switches each. The computation of the inner product of two positive vectors of N item each consisting of m bits takes only [log/sub 3/ (mN/7)]+1 broadcasts, plus a carry-save and a carry-propagate additions.<>
INDEX TERMS
adders, carry logic, digital arithmetic, VLSI, system buses, multiplying circuits, shift registers
CITATION

R. Lin and S. Olariu, "A new buses scheme for fast inner-product computation," Proceedings of 1994 28th Asilomar Conference on Signals, Systems and Computers(ACSSC), Pacific Grove, CA, USA, 1995, pp. 1402-1406.
doi:10.1109/ACSSC.1994.471688
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