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Proceedings of 1994 28th Asilomar Conference on Signals, Systems and Computers (1994)
Pacific Grove, CA, USA
Oct. 31, 1994 to Nov. 2, 1994
ISSN: 1058-6393
ISBN: 0-8186-6405-3
pp: 1398-1401
V.G. Oklobdzija , Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
ABSTRACT
This paper examines the design of a fast carry-propagate adder under the condition of non-equal input signals arrival. This is a common case encountered in the fast parallel multipliers where a carry-propagate adder is deployed to produce the final product. It is shown that the rules used in the past are not valid and do not result in the fastest adder. We present the analysis of those conditions and provide the rules for the fast carry-propagate adder design.<>
INDEX TERMS
adders, digital arithmetic, carry logic
CITATION

V. Oklobdzija, "Design and analysis of fast carry-propagate adder under non-equal input signal arrival profile," Proceedings of 1994 28th Asilomar Conference on Signals, Systems and Computers(ACSSC), Pacific Grove, CA, USA, 1995, pp. 1398-1401.
doi:10.1109/ACSSC.1994.471687
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