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Proceedings of 1994 28th Asilomar Conference on Signals, Systems and Computers (1994)
Pacific Grove, CA, USA
Oct. 31, 1994 to Nov. 2, 1994
ISSN: 1058-6393
ISBN: 0-8186-6405-3
pp: 1388-1392
C.M. Conway , Nat. Instrum. Corp., Austin, TX, USA
E.E. Swartzlander , Nat. Instrum. Corp., Austin, TX, USA
ABSTRACT
The Booth (1951) multiplier represents an efficient and simple way to multiply signed binary numbers. This paper describes an improvement to the standard implementation of a Booth multiplier at any radix. More specifically, it compares VHDL implementations of conventional radix 2, 4, 8, 16, and 32 Booth multipliers against multipliers with the product select circuitry added. VHDL models of the multipliers are analyzed and conclusions are drawn. Estimates of area gain and speedup indicate that this multiplier scheme has significant advantages at lower radices and, at higher radices, still maintains a relative advantage over the radix 2 implementation.<>
INDEX TERMS
multiplying circuits, hardware description languages, digital arithmetic
CITATION

C. Conway and E. Swartzlander, "Product select multiplier," Proceedings of 1994 28th Asilomar Conference on Signals, Systems and Computers(ACSSC), Pacific Grove, CA, USA, 1995, pp. 1388-1392.
doi:10.1109/ACSSC.1994.471685
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