Proceedings of 1994 28th Asilomar Conference on Signals, Systems and Computers (1994)
Pacific Grove, CA, USA
Oct. 31, 1994 to Nov. 2, 1994
G. Liersch , Dept. of Electron. Eng., La Trobe Univ., Bundoora, Vic., Australia
C. Dick , Dept. of Electron. Eng., La Trobe Univ., Bundoora, Vic., Australia
The number of usable gates in field programmable gate array (FPGA) logic has recently reached a level which allows their use as computational structures in digital signal processing (DSP) applications. This paper reports on the development of a scalable computing architecture based on Xilinx (CMOS) XC4010 FPGAs for real-time digital signal processing. The architecture requirements for efficient implementation of common DSP algorithms on FPGA platforms are considered. An analysis of the implementation and performance of a high-bandwidth finite impulse response (FIR) filter is presented. A second design using data requantization and spectral shaping to achieve higher order filters is also described.<
signal processing, field programmable gate arrays, FIR filters, spectral analysis, quantisation (signal), reconfigurable architectures, CMOS logic circuits, real-time systems
G. Liersch and C. Dick, "Reconfigurable gate array architectures for real time digital signal processing," Proceedings of 1994 28th Asilomar Conference on Signals, Systems and Computers(ACSSC), Pacific Grove, CA, USA, 1995, pp. 1383-1387.