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Proceedings of 1994 28th Asilomar Conference on Signals, Systems and Computers (1994)
Pacific Grove, CA, USA
Oct. 31, 1994 to Nov. 2, 1994
ISSN: 1058-6393
ISBN: 0-8186-6405-3
pp: 1036-1040
E. Abdel-Raheem , Dept. of Electr. & Comput. Eng., Victoria Univ., BC, Canada
F. El-Guibaly , Dept. of Electr. & Comput. Eng., Victoria Univ., BC, Canada
A. Antoniou , Dept. of Electr. & Comput. Eng., Victoria Univ., BC, Canada
ABSTRACT
Array processor implementations are obtained (using the signal flow graph) for linear-phase FIR filters. Three structures are reported in which the inputs are pipelined and/or broadcast and the outputs are pipelined. A novel structure is obtained in which the outputs are localized in separate processing elements. A comparison among the resulting structures is performed based on the sampling rate, the latency, and the communication overhead perspectives. A new fixed-point array-multiplier design is then presented. The new processor can perform an add-multiply-accumulate operation in the same time as a simple multiplier. It increases the speed of operation without incurring extra silicon area or introducing extra latency to the system.<>
INDEX TERMS
VLSI, parallel architectures, FIR filters, signal sampling, multiplying circuits, digital arithmetic, signal flow graphs, filtering theory, delay circuits
CITATION

E. Abdel-Raheem, F. El-Guibaly and A. Antoniou, "VLSI array processors for linear-phase FIR filters," Proceedings of 1994 28th Asilomar Conference on Signals, Systems and Computers(ACSSC), Pacific Grove, CA, USA, 1995, pp. 1036-1040.
doi:10.1109/ACSSC.1994.471617
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